Testing structure and method for high density PLDs which have flexible logic built-in blocks

A structure for high density programmable logic device programming, verification and testing comprising:

• a column address shift register and address decoder for shifting in column address, to select the column of the said high density programmable logic device memory to be programmed, verified or tested;
• a row data shift register for shifting in row data, to control a row selection and word line driver of the said high density programmable logic device memory to be programmed, verified or tested;
• controlling means for switching said high density programmable logic device memory between said testing, verifying and programming state;
• a control gate voltage generator for generating different control gate voltages according to said programming, verifying and testing operation;
• a high voltage generator for generating the high voltage needed in said programming, verifying and testing operation;
• a test address shift register for shifting in the address for testing column address decoder;
• an instruction register and instruction decoder for selecting and controlling said programming, verifying and testing operations of said programmable logic device;
• a state controller for controlling said address shift register, said data shift register, said controlling means and said instruction register;
• a preloading shift register for preloading the states of the normal operation registers in functional testing;
• and
• an external control gate voltage input pin for supplying control gate voltage externally for said cell current testing operation.

A method for programming, verifying and testing a high density programmable logic device under a universal supporting structure, said method comprising:

• erasing all for bulk erasing said high density programmable logic device;
• writing all for bulk writing said high density programmable logic device;
• bit programming for programming said high density programmable logic device bit by bit;
• bit verification for verifying said high density programmable logic device bit by bit;
• checker board testing for testing said high density programmable logic device written in checker board and reverse checker board pattern;
• cell current testing for measuring said high density programmable logic device cell current;
• soft writing for adjusting internal writing voltage of said high density programmable logic device;
• and
• column address decoding test for testing column address decoder of said high density programmable logic device.

A high density programmable logic device for implementing a configurable logic function, and having a universal structure supporting a serial algorithm for programming, verifying and testing, said high density programmable logic device comprising:

• a plurality of programmable logic circuits for implementing said configurable logic function;
• means for selecting a location of memory cells to be programmed, verified and tested in said high density programmable logic device;
• means for controlling said testing functions of said high density programmable logic device;
• an instruction register and instruction decoder for selecting and controlling said programming, verifying and testing operations of said programmable logic device;
• and
• a state controller for controlling the operation of said high density programmable logic device.