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US 5,970,004 AGranted
Semiconductor memory device allowing test regardless of spare cell arrangement
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKazuhiko Takami, Kiyoomi Oshigoe, Mikio Asakura
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Abstract
A semiconductor memory device according to the present invention includes a block determining portion determining a difference in arrangement between a normal cell and a spare cell which replaces it, a data scramble controlling circuit generating a scramble ON signal when a normal cell is replaced by a spare cell and the spare cell stores inverted data, a scramble circuit inverting data to be written in response to the scramble ON signal, and a scramble circuit inverting data to be read in response to the scramble ON signal.
Claims5
A semiconductor memory device, comprising:
- a word line;
- a spare word line;
- a plurality of bit lines crossing said word line and said spare word line;
- at least one memory cell arranged at crossings of said word line and said bit lines;
- at least one spare cell arranged at crossings of said spare word line and said bit lines;
- data inverting means for generating an inverting signal for inverting data when said memory cell is replaced by said spare cell and said spare cell stores data inverted with respect to data stored in said memory cell;
- inverse writing means for inverting data to be written to said spare cell according to said inverting signal supplied from said data inverting means when data is written to the spare cell storing said inverted data;
- and
- inverse reading means for inverting data to be read out of said spare cell according to said inverting signal supplied from said data inverting means when data is read out of the spare cell storing said inverted data.
6 more elements
Dependencies are inferred from the claim text.