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US 5,970,003 AGranted
Semiconductor memory device
AssigneesHitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
InventorsShinichi Miyatake, Shuuichi Kubouchi
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprising at least one memory mat comprised of a plurality of memory cells respectively provided at points where a plurality of word lines and spare word lines respectively intersect a plurality of bit lines and spare bit lines placed so as to intersect the word lines and spare word lines. In the semiconductor memory device, a plurality of fuse means allowed to open or remain unopen in accordance with stored information encoded with respect to addresses for specifying defective word lines or defective bit lines are used to control gate means based on their corresponding complementary signals. Thus, the gate means transmit signals for selecting their corresponding word lines or bit lines to thereby produce coincidence/non-coincidence signals.
Claims18
A semiconductor memory device comprising:
- a memory mat including a plurality of memory cells respectively provided at points where a plurality of word lines and spare word lines intersect a plurality of bit lines and spare bit lines placed so as to intersect said plurality of word lines and spare word lines, respectively;
- a plurality of fuses allowed to open or remain unopen in accordance with stored information encoded with respect to addresses for specifying defective word lines or defective bit lines;
- a plurality of gate circuits which receive a plurality of complementary signals respectively produced according to the presence or absence of opening of said plurality of fuses, and transmit a signal for selecting a word line or bit lines to thereby produce one of coincidence and non-coincidence signals;
- and
- a plurality of defect relief circuits each switching said defective word lines or said defective bit lines to said spare word lines or bit lines in response to a coincidence signal produced through said gate circuits,
- wherein said encoded stored information is formed so as to have binary weights and said gate circuits comprise transfer gate MOSFETs configured in tree form, which are switch-controlled by complementary signals corresponding to the binary weights, and transmit said select signal through said tree-shaped transfer gate MOSFETs.
3 more elements
A semiconductor memory device comprising:
- a plurality of memory mats each including a plurality of memory cells provided at points where a plurality of word lines and spare word lines intersect a plurality of bit lines and spare bit lines placed so as to intersect said plurality of word lines and spare word lines, respectively;
- a plurality of fuses each allowed to open or remain unopen in accordance with stored information encoded with respect to first addresses for specifying a defect-existing memory mat of said plurality of memory mats;
- gate circuits which receive signals respectively formed according to the presence or absence of opening of said plurality of fuses and signals formed based on second addresses supplied from the outside, said each gate circuit outputting a coincidence signal when said first and second addresses coincide with each other;
- and
- defect relief circuit which switches defective bit lines lying within each memory mat to spare bit lines based on said coincidence signal.
2 more elements
A semiconductor memory device comprising:
- a plurality of memory mats, each memory mat including a plurality of memory cells provided at points where a plurality of word lines and spare word lines intersect a plurality of bit lines and spare bit lines placed so as to intersect said plurality of word lines and spare word lines, respectively;
- a plurality of first fuses each allowed to open or remain unopen in accordance with first stored information encoded with respect to a first address for specifying a defect-existing memory mat of said plurality of memory mats;
- a first gate circuit which receives signals respectively formed according to the presence or absence of opening of said plurality of first fuses and signals formed based on a second address supplied from the outside, said first gate circuit outputting a first coincidence signal when said first and second addresses coincide with each other;
- a plurality of second fuses allowed to open or remain unopen in accordance with second stored information encoded with respect to a third address for specifying defective bit lines lying within a predetermined memory mat;
- a second gate circuit which receives signals formed according to the presence or absence of opening of said second fuses and signals formed based on a fourth address supplied from the outside, said second gate circuit outputting a second coincidence signal when said third and fourth addresses coincide with each other and said first coincidence signal is outputted;
- and
- a defect relief circuit which switches defective bit lines lying within said predetermined memory mat to spare bit lines based on said second coincidence signal.
4 more elements
A semiconductor device comprising:
- a memory mat including a plurality of memory cells respectively provided at points where a plurality of word lines and spare word lines intersect a plurality of bit lines and spare bit lines placed so as to intersect said plurality of word lines and spare word lines, respectively;
- a plurality of fuses allowed to open in accordance with stored information encoded with respect to addresses for specifying defective word lines or defective bit lines;
- a plurality of gates which receive a plurality of complementary signals respectively produced according to the presence or absence of opening of said plurality of fuses, and transmitting signals for selecting their corresponding word lines or bit lines to thereby produce coincidence and/or non-coincidence signals;
- and
- a plurality of defect relief circuits each switching said defective word lines or said defective bit lines to said spare word lines or bit lines in response to a coincidence signal produced through said gates, wherein said encoded stored information is formed so as to have binary weights and said gates comprise transfer gate MOSFETs configured in tree form, which are switch-controlled by complementary signals corresponding to the binary weights, and which transmit said select signals for selecting word lines or bit lines through said tree-shaped transfer gate MOSFETs.
2 more elements
A semiconductor memory device comprising:
- a memory mat including a plurality of memory cells respectively provided at points where a plurality of word lines and spare word lines intersect a plurality of bit lines and spare bit lines placed so as to intersect said plurality of word lines and spare word lines, respectively;
- a plurality of fuses allowed to open in accordance with stored information encoded with respect to addresses for specifying defective word lines or defective bit lines;
- a plurality of gates which receive a plurality of complementary signals respectively produced according to the presence or absence of opening of said plurality of fuses, and transmitting signals for selecting their corresponding word lines or bit lines to thereby produce coincidence and/or non-coincidence signals;
- and
- a plurality of defect relief circuits each switching said defective word lines or said defective bit lines to said spare word lines or bit lines in response to a coincidence signal produced through said gates, wherein said encoded stored information is formed so as to have binary weights and said gates are respectively comprised of combinations of logic gate circuits for receiving complementary signals corresponding to the binary weights and signals for selecting the word lines or bit lines, said signal having binary weights in association with the complementary signals.
2 more elements
A semiconductor memory device comprising:
- a memory mat including a plurality of memory cells respectively provided at points where a plurality of word lines and spare word lines intersect a plurality of bit lines and spare bit lines placed so as to intersect said plurality of word lines and spare word lines, respectively;
- a plurality of fuses allowed to open in accordance with stored information encoded with respect to addresses for specifying defective word lines or defective bit lines;
- a plurality of gates which receive a plurality of complementary signals respectively produced according to the presence or absence of opening of said plurality of fuses, and transmitting signals for selecting their corresponding word lines or bit lines to thereby produce coincidence and/or non-coincidence signals;
- and
- a plurality of defect relief circuits each switching said defective word lines or said defective bit lines to said spare word lines or bit lines in response to a coincidence signal produced through said gates, wherein said encoded stored information is formed so as to have binary weights, and said gates are switch-controlled by logic circuits for decoding complementary signals corresponding to the binary weights, and signals outputted from the logic circuits to thereby transfer signals for selecting the corresponding word line or bit lines.
2 more elements
Dependencies are inferred from the claim text.