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US 5,970,001 AGranted
Dynamic RAM provided with a defect relief circuit
AssigneeHitachi, Ltd.
InventorsHiromasa Noda, Kenji Nishimoto, Yoshitaka Kinoshita, Masakazu Aoki
Life of this patent
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Abstract
An X address buffer for generating an internal address signal by capturing an X address signal input from an address terminal is brought into an operating state before an external control clock is input. A redundancy address comparator for detecting a match/mismatch signal by comparing the generated internal address signal with a stored X-system defective address is used as a static circuit. Thereby, the redundancy address comparator starting operation is accelerated and as a result, acceleration of the reading operation is achieved.
Claims22
A dynamic RAM comprising:
- an external address terminal to which X- and Y-system address signals are input in time series;
- an external clock terminal for receiving a clock signal;
- a controller which generates a timing signal necessary for internal operations in accordance with a control signal input synchronously with the clock signal;
- an X address buffer which generates an internal address signal by capturing an X address signal input from the external address terminal;
- an address comparator including a static circuit which outputs a match/mismatch signal by comparing the internal address signal generated by the X address buffer with an X-system defective address;
- a word driver which selects a word line of a normal circuit in accordance with a mismatch signal output from the address comparator;
- and
- a redundancy word driver which selects a word line of a redundant circuit in accordance with a match signal output from the address comparator.
5 more elements
A dynamic RAM comprising:
- an external address terminal to which X- and Y-system address signals are input in time series;
- an external clock terminal for receiving a clock signal;
- an external terminal for receiving a control signal;
- a controller which generates a timing signal necessary for the internal operations in accordance with the control signal captured synchronously with the clock signal;
- a first X address buffer which generates a first internal address signal by capturing an X address signal input from the external address terminal;
- a second X address buffer which generates a second internal address signal by receiving an X address signal input from the external address terminal and holding the X address signal in accordance with a timing signal generated by the controller;
- a comparator including a static circuit which outputs a match/mismatch signal by comparing the first internal address signal generated by the first X address buffer with a stored X-system defective address;
- a word driver which selects a word line of a normal circuit in accordance with a mismatch signal output from the comparator;
- and
- a redundancy word driver which selects a word line of a redundant circuit in accordance with a match signal output from the comparator.
7 more elements
A dynamic RAM comprising:
- an address terminal to which an X-system address signal and a Y-system address signal are input in time series;
- a control circuit which generates a timing signal necessary for internal operations in accordance with a control signal supplied from an external terminal;
- an X address buffer which generates an internal address signal by capturing an X address signal input from the address terminal;
- a redundancy address comparator including a static circuit which detects a match/mismatch signal by receiving internal address signal generated by the X address buffer and compares the internal address signal with a stored X-system defective address;
- a predecoder which generates a predecode signal by receiving an internal address signal generated by the X address buffer and holds the predecode signal in accordance with an operation timing signal generated by the control circuit;
- a word driver which selects a word line of a normal circuit in accordance with the combination of the predecode signals and the combination of mismatch signals supplied from the address comparator;
- and
- a redundancy word driver which selects a word line of a redundant circuit in accordance with a match signal supplied from the address comparator.
5 more elements
A dynamic RAM comprising:
- an address terminal to which an X-system address signal and a Y-system address signal are input in time series;
- a control circuit which generates a timing signal necessary for internal operations in accordance with a control signal supplied from an external terminal;
- a first X address buffer which generates a first internal address signal by capturing the X address signal input from the address terminal;
- a second X address buffer which generates a second internal address signal by receiving an X address signal input from the address terminal and holds the X address signal in accordance with a timing signal generated by the control circuit;
- a redundancy address comparator including a static circuit which detects a match/mismatch signal by receiving a first internal address signal generated by the first X address buffer and compares the address signal with a stored X-system defective address;
- a predecoder which generates a predecode signal by receiving a second internal address signal generated by the second X address buffer;
- a word driver which selects a word line of a normal circuit in accordance with the combination of the predecode signals and the combination of mismatch signals supplied from the address comparator;
- and
- a redundancy word driver which selects a word line of a redundant circuit in accordance with a match signal supplied from the address comparator.
6 more elements
Dependencies are inferred from the claim text.