Merged memory logic integrated circuits including buffers driven by adjustably delayed clock signals

#The present invention relates to integrated circuits, more particularly, to buffers and related circuits for integrated circuits.

#Merged memory logic (MML) integrated circuits are conventionally used in lightweight or compact systems to provide high performance and reduced power consumption. A typical MML integrated circuit includes memory, e.g., a dynamic random access memory (DRAM) or a static random access memory (SRAM), along with logic appropriate to control the memory, combined on a single chip. Typically, the logic controls the writing and reading of data in the memory.

#FIG. 1 is a block diagram of a conventional semiconductor memory integrated circuit 101. The integrated circuit 101 includes an input terminal clock buffer 111, an input buffer 121, an output terminal clock buffer 141, an output buffer 131 and a memory 151. The input terminal clock buffer 111 generates an internal clock signal PCLK in response to an external clock signal CLK. The input buffer 121 transmits received data DI1 to the memory 151 in response to the internal clock signal PCLK. The input terminal clock buffer 111 includes an internal clock generator 113 for generating the internal clock signal PCLK from the external clock signal CLK, the internal clock signal being delayed by an interval introduced by a delay 115.

#FIG. 1 is schematic diagram illustrating buffer circuitry in a conventional memory integrated circuit.

#FIG. 2 is a schematic diagram of a merged memory logic (MML) integrated circuit illustrating a buffer circuit according to an embodiment of the present invention.

#FIG. 3 is a schematic diagram of a control circuit and switch for an adjustable clock generator according to an embodiment of the present invention.

#The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

#Referring to FIG. 2, a merged memory logic (MML) integrated circuit 201 includes a logic circuit 211, a memory 221, a first adjustable clock generator 231, an input buffer 241, an output buffer 251 and a second adjustable clock generator 261. The logic circuit 211 generates a clock signal CLK. The first adjustable clock generator 231 receives the clock signal CLK and control signals PSW1-3 from a programmable logic circuit 210 in the logic circuit 211 and provides a first adjustably delayed clock signal PCLK to the input buffer 241 responsively thereto. The second adjustable clock generator 261 receives the clock signal CLK and control signals PSW4-6 from the programmable logic circuit 210 and provides a second adjustably delayed clock signal DQCLK to the output buffer 251 responsively thereto. The programmable logic circuit produces the control signals PSW1-6 according to a program 212 applied to the programmable logic circuit 210.

#The first adjustable clock generator 231 includes a clock generator 233 and first, second and third delay circuits 271, 272 and 273 connected to first, second and third switches 281, 282 and 283, respectively. The clock generator 233 generates an output clock signal 234 from the input clock signal CLK. The first, second and third delay circuits 271, 272, 273 produce first, second and third delayed clock signals 277, 278, 279, respectively, which are delayed by respective first, second and third predetermined intervals with respect to the output clock signal 234. For example, the second delay circuit 272 may introduce a delay Ti, and the first and third delay circuits 271, 273 may introduce delays T1-.alpha. and T1+.alpha., respectively.