MOS semiconductor device with memory cells each having storage capacitor and transfer transistor

A dynamic random access memory device comprising:

• a plurality of pairs of first and second bit lines each pair of bit lines including a first bit line and a second bit line;
• a plurality of word lines transverse to the bit line pairs to define cross points therebetween;
• an array of memory cells at the cross points, each of said memory cells including a capacitor and a voltage-controlled transistor having a gate electrode coupled to a corresponding one of said word lines associated therewith, said transistor being connected between said capacitor and one of said first and second bit lines;
• sense amplifier circuits connected to said bit line pairs, and having a first common source line and a second common source line;
• decoder means connected to said word lines, for selecting one of said word lines;
• first voltage generator means connected to said first common source line, for selectively supplying said first common source line with a first voltage which defines a high-level voltage for said bit line pairs;
• and
• second voltage generator means connected to said second common source line, for generating a second voltage which defines a low-level voltage for said bit line pairs, and for selectively supplying said second voltage to said second common source line, said second voltage being higher than a ground potential.
• wherein said transistor has a threshold voltage which is decreased due to a decrease in impurity concentration in a channel region of said transistor.