US 5,969,996 AGranted

Semiconductor memory device and memory system

AssigneeHiachi, Ltd.

InventorsMasaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame

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Abstract

Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.

Claims43

Dependent claims

A memory system comprising:

a plurality of dynamic RAMs each having a plurality of memory arrays in each of which dynamic memory cells, each including an address selection MOSFET and an information storage capacitor coupled thereto, are respectively provided at points of intersection of complementary bit line pairs of folded-bit line type and word lines in matrix form;
and
a control chip including a data converter, which performs data conversion for validating memory cells in a pair of dynamic RAMs upon simultaneously-selecting a specific write operation, associating a logic 1 of a write signal with a state in which an electric charge exists in said each capacitor and associating a logic 0 of the write signal with a state in which no electric charge exists in said each capacitor, which performs data conversion for validating the memory cells in the pair of dynamic RAMs upon simultaneously-selecting a specific read operation, allowing the state of existence of the charge in the capacitor in said each dynamic memory cell to correspond to a logic 1 of a read signal and allowing the charge-free state of said each capacitor to correspond to a logic 0 of the read signal, and which outputs a signal corresponding to the OR of the data-converted two read signals produced from the two different dynamic RAMs as a read signal,
wherein said plurality of dynamic RAMs and said control chip are provided on a single mounted substrate.

1 more element

A memory system comprising:

an even number of semiconductor memory devices provided on a single mounted substrate, each including:
a plurality of memory arrays each having dynamic memory cells each including an address selection MOSFET and an information storage capacitor coupled thereto, said memory cells being provided in matrix form at points of intersection of each individual pair of complementary bit lines and word lines;
and
a data conversion circuit which performs data conversion such that in a write operation mode, a write signal having one level brings the information storage capacitor in said each memory cell into a charge-existing state and a write signal having the other level brings the information storage capacitor into a charge-free state and which performs data conversion associated with said write operation mode in a read mode,
whereby the same data is written into the semiconductor memory devices of said even number of semiconductor memory devices, which are provided two by two and a logical OR signal is output from said each pair of two semiconductor memory devices.

2 more elements

A memory system comprising:

(i) a first chip comprising
(a) a first word line,
(b) a second word line,
(c) a first complementary data line pair having a first data line and a second data line,
(d) a first memory cell provided so as to correspond to a point of intersection of said first word line and said first data line,
(e) a second memory cell provided so as to correspond to a point of intersection of said second word line and said second data line, and
(f) a first sense amplifier connected to said first data line and to said second data line;
(ii) a second chip comprising
(a) a third word line,
(b) a fourth word line,
(c) a second complementary data line pair having a third data line and a fourth data line,
(d) a third memory cell provided so as to correspond to a point of intersection of said third word line and said third data line,
(e) a fourth memory cell provided so as to correspond to a point of intersection of said fourth word line and said fourth data line, and
(f) a second sense amplifier connected to said third data line and to said fourth data line;
and
(iii) a circuit outputting a signal,
wherein said signal is a first voltage when read data transferred from said first memory cell to said first data line is high in level and read data transferred from said third memory cell to said third data line is high in level,
wherein said signal is said first voltage when read data transferred from said first memory cell to said first data line is high in level and read data transferred from said third memory cell to said third data line is low in level,
wherein said signal is said first voltage when read data transferred from said first memory cell to said first data line is low in level and read data transferred from said third memory cell to said third data line is high in level, and
wherein said signal is a second voltage when read data transferred from said first memory cell to said first data line is low in level and read data transferred from said third memory cell to said third data line is low in level.

17 more elements

A memory system comprising:

a first memory array comprising a plurality of first memory cells;
a second memory array comprising a plurality of second memory cells;
and
a circuit connected to said first memory array and to said second memory array so as to output a signal therefrom,
wherein said signal is a first voltage when data stored in a respective first memory cell is high in level and data stored in a respective second memory cell is high in level in a case in which both said first memory cell and said second memory cell are accessed for reading out,
wherein said signal is a first voltage when data stored in said first memory cell is high in level and data stored in said second memory cell is low in level in a case in which both said first memory cell and said second memory cell are accessed for reading out,
wherein said signal is a first voltage when data stored in said first memory cell is low in level and data stored in said second memory cell is high in level in a case in which both said first memory cell and said second memory cell are accessed for reading out, and
wherein said signal is a second voltage when data stored in said first memory cell is low in level and data stored in said second memory cell is low in level in a case in which both said first memory cell and said second memory cell are accessed for reading out.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/144,526Filed 31 Aug 1998 · division
Priority: JP 7-12589225 Apr 1995
Granted: 19 Oct 1999
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 7/1069
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: i/O lines read…
G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…
G11C 7/1051
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…
G11C 11/406
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles