Static semiconductor memory device having active mode and sleep mode
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorChikayoshi Morishima
Life of this patent
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Abstract
A power supply control circuit of an SRAM cuts off supply of power supply voltage to any component other than memory cells and a word line potential fix circuit in a sleep period in which only retention of data is carried out. The word line potential fix circuit fixes a word line at a non-selection level in the sleep period. The potential on the word line never becomes unstable in the sleep period so that data in the memory cell is never destroyed. Accordingly, a static semiconductor memory device consuming less power and having a high data retention ability can be provided.
Claims8
A static semiconductor memory device having an active mode for reading/writing and holding data, and a sleep mode for holding data and prohibiting data from being read and written, comprising:
- a memory cell array including a plurality of memory cells arranged in rows and columns, word lines provided correspondingly to respective rows, and bit line pairs provided correspondingly to respective columns;
- a read/write circuit selecting any of the memory cells in said memory cell array according to an address signal for reading/writing data from/into the memory cell;
- power supply control means for supplying power supply voltage to said read/write circuit in said active mode, and cutting off supply of the power supply voltage to said read/write circuit in said sleep mode;
- and
- switch means provided correspondingly to each word line, connected between the corresponding word line and a line of reference potential, and rendered conductive in said sleep mode for fixing the corresponding word line in a non-selected state.
A static semiconductor memory device having an active mode for reading/writing and holding data, and a sleep mode for holding data and prohibiting data from being read and written, comprising:
- a memory cell array including a plurality of memory cells arranged in rows and columns, word lines provided correspondingly to respective rows, and bit line pairs provided correspondingly to respective columns;
- a read/write circuit selecting any of the memory cells in said memory cell array according to an address signal for reading/writing data from/into the memory cell;
- a first transistor connected to said read/write circuit, for supplying power supply voltage to said read/write circuit in said active mode, and cutting off supply of the power supply voltage to said read/write circuit in said sleep mode;
- and
- second transistors provided correspondingly to respective word lines, each second transistor being connected between the corresponding word line and a line of reference potential, and being rendered conductive in said sleep mode for fixing the corresponding word line in a non-selected state.
Dependencies are inferred from the claim text.