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US 5,969,992 AGranted
EEPROM cell using P-well for tunneling across a channel
AssigneeVantis Corporation
InventorsSunil D. Mehta, Xiao-Yu Li
Life of this patent
Estimating the term…
Abstract
An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a P-well of a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.
Claims19
An EEPROM cell, comprising:
- a semiconductor substrate, said semiconductor substrate having an N conductivity type;
- a well formed in said semiconductor substrate, said well having a P conductivity type;
- a tunneling transistor formed in said well, said tunneling transistor having a tunneling source, a tunneling drain and a tunneling channel between said tunneling source and said tunneling drain, said tunneling drain and said tunneling source having said N conductivity type;
- a tunnel oxide layer overlying said tunneling channel, said tunneling source and said tunneling drain;
- a program junction region formed in said well, said program junction region separated from said tunneling transistor by a first oxide, said program junction region having said N conductivity type;
- a program junction oxide layer overlying said program junction region;
- a sense transistor formed in said well and separated from said program junction region by a second oxide, said sense transistor having a sense source, a sense drain and a sense channel between said sense source and said sense drain, said sense source and said sense drain having said N conductivity type;
- a sense tunnel oxide layer overlying said sense channel, said sense source and said sense drain;
- a read transistor formed in said well, said read transistor electrically connected to said sense transistor through said sense drain;
- and
- a floating gate overlying said tunnel oxide layer, said program junction oxide layer and said sense tunnel oxide layer.
8 more elements
An EEPROM cell, comprising:
- a semiconductor substrate, said semiconductor substrate having an N conductivity type;
- a well formed in said semiconductor substrate, said well having a P conductivity type;
- a tunneling transistor formed in said well, said tunneling transistor having a tunneling source, a tunneling drain and a tunneling channel between said tunneling source and said tunneling drain, said tunneling drain and said tunneling source having said N conductivity type, said tunneling source, tunneling drain, and well being electrically connected to a word bit line;
- a tunnel oxide layer overlying said tunneling channel, said tunneling source and said tunneling drain;
- a program junction region formed in said well, said program junction region separated from said tunneling transistor by a first oxide, said program junction region having said N conductivity type, said program junction region being electrically connected to an array control gate;
- a program junction oxide layer overlying said program junction region;
- a sense transistor formed in said well and separated from said program junction region by a second oxide, said sense transistor having a sense source, a sense drain and a sense channel between said sense source and said sense drain, said sense source and said sense drain having said N conductivity type, said sense source being electrically connected to a product term ground;
- a sense tunnel oxide layer overlying said sense channel, said sense source and said sense drain;
- a read transistor formed in said well, said read transistor electrically connected to said sense transistor through said sense drain, said read transistor having a read source, a read drain, and a read channel between said read source and said read drain, said read drain having an N conductivity type and being electrically connected to a product term;
- a read gate oxide layer overlying said read channel;
- and
- a floating gate overlying said tunnel oxide layer, said program junction oxide layer and said sense tunnel oxide layer, wherein electron tunneling through said tunnel oxide layer overlying said tunneling channel occurs upon incurrence of a sufficient voltage potential between said floating gate and said tunneling channel, and wherein electron tunneling through said sense tunnel oxide layer overlying said sense channel occurs upon incurrence of a sufficient voltage potential between said floating gate and said sense channel.
9 more elements
Dependencies are inferred from the claim text.