Method of erasing a flash EEPROM memory cell array optimized for low power consumption

A method of erasing an array or a party of an array of nonvolatile memory cells,

• said cells comprising a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of the drain region, and over a portion of said channel with a thin oxide layer therebetween, further referred to as the floating-gate channel, and ending over said channel, a control gate extending over another portion of the channel region, further referred to as the control-gate channel, and over a portion of the source region, an additional program gate capacitively coupled through a dielectric layer to said floating gate,
• said array or part of an array comprising a number of rows of said cells, sharing a common substrate, wherein said control gates of said cells on the same row are connected to a common wordline, and said program gates of said cells are connected to a common program line,
• said method comprising the steps of:
• (i) applying a first voltage comprising an on-chip generated negative voltage in the order of -7V simultaneously to at least one of said program lines and to at least one of said wordlines thereby coupling a negative voltage to said floating gates of said cells that share both said wordline and said program line;
• and
• (ii) applying a second voltage to said common substrate of said cells, said second voltage being equal to the supply voltage,
• to thereby cause a tunneling current of electrons to flow from said floating gates of said cells towards said substrate of said cells while achieving simultaneous erasure of said memory cells sharing both said wordline and said program line without the need for high negative voltages nor a high power consumption from the supply voltage.

A method of erasing an array or part of an array of nonvolatile memory cells,

• said cells comprising a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of the drain region with a thin oxide layer therebetween, and over a portion of said channel, further referred to as the floating-gate channel, and ending over said channel, a control gate extending over another portion of the channel region, further referred to as the control-gate channel, and over a portion of the source region, an additional program gate capacitively coupled through a dielectric layer to said floating gate,
• said array or part of an array comprising a number of rows of said cells, wherein said control gates of said cells on the same row are connected to a common wordline, and said program gates of said cells are connected to a common program line,
• said method comprising the steps of:
• (i) applying a first voltage comprising an on-chip generated negative voltage in the order of -7V simultaneously to at least one of said program lines and to at least one of said wordlines thereby coupling a negative voltage to said floating gates of said cells that share both said wordline and said program line;
• and
• (ii) applying a second voltage to said drain regions of said cells, said second voltage being an on-chip generated voltage higher than the supply voltage, to thereby cause a tunneling current of electrons to flow from said floating gates of said cells towards said drain junctions of said cells while achieving simultaneous erasure of said memory cells sharing both said wordline and said program line without the need for high negative voltages.

A method of erasing an array or a party of an array of nonvolatile memory cells,

• said cells comprising a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of the drain region, and over a portion of said channel with a thin oxide layer therebetween, further referred to as the floating-gate channel, and ending over said channel, a control gate extending over another portion of the channel region, further referred to as the control-gate channel, and over a portion of the source region, an additional program gate capacitively coupled through a dielectric layer to said floating gate,
• said array or part of an array comprising a number of rows of said cells, sharing a common substrate, wherein said control gates of said cells on the same row are connected to a common wordline, and said program gates of said cells are connected to a common program line,
• said method comprising the steps of:
• (i) applying a first voltage comprising an on-chip generated negative voltage in the order of -7V simultaneously to at least one of said program lines and to at least one of said wordlines thereby coupling a negative voltage to said floating gates of said cells that share both said wordline and said program line;
• and
• (ii) applying a second voltage to said common substrate of said cells, said second voltage being an on-chip generated voltage higher than the supply voltage;
• to thereby cause a tunneling current of electrons to flow from said floating gates of said cells towards said substrate of said cells while achieving simultaneous erasure of said memory cells sharing both said wordline and said program line without the need for high negative voltages nor a high power consumption from the supply voltage.