Semiconductor memory device capable of storing plural-bit data in a single memory cell

#1. Field of the Invention

#The present invention relates to a semiconductor memory device for storing data of plural bits in a single memory cell constituted by a single transistor.

#2. Description of the Related Art

#The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

#FIGS. 1A and 1B show a first embodiment of a memory cell according to the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line 1B--1B in FIG. 1A;

#FIGS. 2A and 2B illustrate a step of writing data in the memory cell shown in FIGS. 1A and 1B, in which FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along line 2B--2B in FIG. 2A;

#Preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

#FIGS. 1A and 1B show a first embodiment of a memory cell of the present invention and illustrate a method of writing data in the memory cell. In FIG. 1A, symbol G denotes a gate, S a source, and D a drain. FIG. 1B shows the state of the memory cell prior to data write. Field insulating films 52 and 53 are formed in a surface region of a substrate 51. A gate insulating film 54 is formed between the field insulating films 52 and 53. The gate G is formed on the field insulating films 52 and 53 and gate insulating film 54. Impurities 55 are introduced into the substrate 51 below the field insulating films 52 and 53. Impurities 56 are introduced into a channel region CH within the substrate 51 to set a predetermined threshold voltage.

#For example, when the memory cell is constituted by an N-channel transistor, the threshold voltage of the memory cell may be determined by making use of ion implantation which is performed in a channel region of a peripheral N-channel enhancement transistor to set the threshold voltage of this peripheral transistor. In the present invention, after the gate electrode of the memory cell is formed, impurities are introduced by the ion implantation into the channel region of the memory cell through the gate electrode thereof. The substantial channel width is varied by the introduction of the impurities. Thus, only a manufacturing step of introducing impurities is added, and the delivery date can be made earlier.