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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYuichiro Komiya, Tsukasa Ooishi, Hideto Hidaka, Mikio Asakura
Estimating the term…
The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.
A semiconductor device, comprising:
A semiconductor device, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data input circuits, e.g. write amplifiers, data…
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels:…
Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor: substrate bias generators
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: voltage…
Term ended 3 Jul 2016 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a level converting circuit for converting a level of an input signal, an internal potential generating circuit for generating an internal potential, an internal potential generating unit for generating an internal potential, a semiconductor device and method of manufacturing a transistor. More specifically, it relates to a level converting circuit capable of preventing through current, an internal potential generating circuit providing higher efficiency in generating internal potential, an internal potential generating unit facilitating setting of performance, a highly reliable semiconductor device and to a method of manufacturing a transistor having high breakdown voltage.
2. Description of the Background Art
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
FIG. 1 is a circuit diagram showing a level converting circuit in accordance with a first embodiment of the present invention.
FIG. 2 is a timing chart illustrating the operation of the level converting circuit shown in FIG. 1.
The level converting circuit, the internal potential generating circuit and the internal potential generating unit in accordance with the present invention will be described with reference to the figures.
FIG. 1 shows, in detail, the level converting circuit in accordance with the first embodiment of the present invention.
Referring to FIG. 1, the level converting circuit in accordance with the first embodiment includes a PMOS transistor 1 for cutting current for an input portion, a PMOS transistor 3 for the input portion, an NMOS transistor 5 for the input portion, an NMOS transistors 7 for cutting current for the input portion, a PMOS transistor 9 for cutting current for an output portion, a PMOS transistor 11 for the output portion, an NMOS transistor 13 for the output portion, an NMOS transistor 15 for cutting current of the output portion, and inverters 17 and 19.