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US 5,969,983 AGranted
Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer
AssigneeMicron Technology, Inc.
InventorsRandhir P. S. Thakur, Garry A. Mercaldi, Michael Nuttall
Life of this patent
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Abstract
A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier materials.
Claims9
A memory circuit, comprising:
- first and second supply terminals;
- address, data, and command busses;
- a cell plate;
- an array of memory cells arranged in rows and columns and including digit lines and word lines, the memory cells in each row being coupled to a respective word line and the memory cells in each column being coupled to a respective digit line, each of the memory cells respectively comprising,
- a switch having a control terminal coupled to the respective word line, an access terminal coupled to the respective digit line, and a storage terminal, and
- a storage element having a data terminal coupled to the storage terminal of the switch and having a reference terminal coupled to the cell plate, the storage element comprising,
- a dielectric having first and second opposite sides,
- a first conductive barrier layer adjacent to the first side of the dielectric and coupled to the data terminal, and
- an electrode adjacent to the second side of the dielectric and coupled to the reference terminal;
- an address decoder coupled to the address bus and to the array;
- a read/write circuit coupled to the address decoder and to the array;
- a data input/output circuit coupled to the data bus and to the read/write circuit;
- and
- a control circuit coupled to the command bus, to the address decoder, to the read/write circuit, and to the data input/output circuit.
11 more elements
A memory circuit, comprising:
- first and second supply terminals;
- address, data, and command busses;
- a cell plate;
- an array of memory cells arranged in rows and columns and including digit lines and word lines, the memory cells in each row being coupled to a respective word line and the memory cells in each column being coupled to a respective digit line, each of the memory cells respectively comprising,
- a switch having a control terminal coupled to the respective word line, an access terminal coupled to the respective digit line, and a storage terminal, and
- a storage element having a data terminal coupled to the storage terminal of the switch and having a reference terminal coupled to the cell plate, the storage element comprising,
- a dielectric having first and second opposite sides,
- an electrode adjacent to the first side of the dielectric and coupled to the data terminal, and
- a conductive barrier layer adjacent to the second side of the dielectric and coupled to the reference terminal;
- an address decoder coupled to the address bus and to the array;
- a read/write circuit coupled to the address decoder and to the array;
- a data input/output circuit coupled to the data bus and to the read/write circuit;
- and
- a control circuit coupled to the command bus, to the address decoder, to the read/write circuit, and to the data input/output circuit.
11 more elements
An electronic system, comprising:
- a data input device;
- a data output device;
- and
- computing circuitry coupled to the data input and output devices, the computing circuitry including a memory circuit that includes,
- first and second supply terminals,
- address, data, and command busses,
- a cell plate,
- an array of memory cells arranged in rows and columns and including digit lines and word lines, the memory cells in each row being coupled to a respective word line and the memory cells in each column being coupled to a respective digit line, each of the memory cells respectively comprising,
- a switch having a control terminal coupled to the respective word line, an access terminal coupled to the respective digit line, and a storage terminal, and
- a storage element having a data terminal coupled to the storage terminal of the switch and having a reference terminal coupled to the cell plate, the storage element comprising,
- a dielectric having first and second opposite sides,
- a conductive barrier layer adjacent to the first side of the dielectric and coupled to the data terminal, and
- an electrode adjacent to the second side of the dielectric and coupled to the reference terminal,
- an address decoder coupled to the address bus and to the array,
- a read/write circuit coupled to the address decoder and to the array,
- a data input/output circuit coupled to the data bus and to the read/write circuit, and
- a control circuit coupled to the command bus, to the address decoder, to the read/write circuit, and to the data input/output circuit.
14 more elements
An electronic system, comprising:
- a data input device;
- a data output device;
- and
- computing circuitry coupled to the data input and output devices, the computing circuitry including a memory circuit that includes,
- first and second supply terminals,
- address, data, and command busses,
- a cell plate,
- an array of memory cells arranged in rows and columns and including digit lines and word lines, the memory cells in each row being coupled to a respective word line and the memory cells in each column being coupled to a respective digit line, each of the memory cells respectively comprising,
- a switch having a control terminal coupled to the respective word line, an access terminal coupled to the respective digit line, and a storage terminal, and
- a storage element having a data terminal coupled to the storage terminal of the switch and having a reference terminal coupled to the cell plate, the storage element comprising,
- a dielectric having first and second opposite sides,
- an electrode adjacent to the first side of the dielectric and coupled to the data terminal, and
- a conductive barrier layer adjacent to the second side of the dielectric and coupled to the reference terminal,
- an address decoder coupled to the address bus and to the array,
- a read/write circuit coupled to the address decoder and to the array,
- a data input/output circuit coupled to the data bus and to the read/write circuit, and
- a control circuit coupled to the command bus, to the address decoder, to the read/write circuit, and to the data input/output circuit.
14 more elements
Dependencies are inferred from the claim text.