Ferroelectric memory devices having linear reference cells therein and methods of operating same

A nonvolatile memory device, comprising:

• a bit line;
• a reference bit line;
• a plate line;
• a reference plate line;
• a ferroelectric memory cell containing an access transistor having a source region electrically connected to said bit line and a ferroelectric storage capacitor having a plate electrode electrically connected to said plate line;
• a reference cell containing an access transistor having a source region electrically connected to said reference bit line and a linear storage capacitor having a plate electrode electrically connected to said reference plate line;
• and
• a sense amplifier having first and second inputs electrically coupled to said bit line and said reference bit line, respectively.

In an integrated circuit memory device containing a ferroelectric memory cell, a linear reference cell and a sense amplifier electrically coupled to the ferroelectric memory cell and the linear reference cell by a bit line and reference bit line, respectively, a method of reading a state of the ferroelectric memory cell, comprising the steps of:

• discharging a linear storage capacitor in the linear reference cell;
• driving the bit line to a first potential by electrically connecting a storage electrode of a ferroelectric capacitor in the ferroelectric memory cell to the bit line while simultaneously driving a plate electrode of the ferroelectric capacitor to a first plate potential;
• driving the reference bit line to a second potential by electrically connecting a storage electrode of the discharged linear storage capacitor in the linear reference cell to the reference bit line while simultaneously driving a plate electrode of the discharged linear storage capacitor to a second plate potential;
• and
• driving the bit line and reference bit line to respective opposite potentials by sensing and amplifying a difference in potential between the bit line and reference bit line.

In an integrated circuit memory device containing a ferroelectric memory cell, a linear reference cell and a sense amplifier electrically coupled to the ferroelectric memory cell and the linear reference cell by a bit line and reference bit line, respectively, a method of operating the memory device, comprising the steps of:

• driving the bit line to a first potential by electrically connecting a storage electrode of a ferroelectric capacitor in the ferroelectric memory cell to the bit line while simultaneously driving a plate electrode of the ferroelectric capacitor to a first plate potential;
• driving the reference bit line to a second potential by electrically connecting a storage electrode of the linear storage capacitor in the linear reference cell to the reference bit line while simultaneously driving a plate electrode of the linear storage capacitor to a second plate potential;
• and
• driving the bit line and reference bit line to respective opposite potentials by sensing and amplifying a difference in potential between the bit line and reference bit line.