Semiconductor memory device employing ferroelectric memory cell, attaining low power consumption while preventing deterioration of ferroelectric
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakashi Kono
Life of this patent
Estimating the term…
Abstract
A memory cell array of a semiconductor memory device is split into memory blocks. A DRAM/nonvolatile mode switching circuit makes each memory cell operate similarly to a DRAM when each memory block is accessed from the exterior while making each memory cell operate as a nonvolatile memory cell to require no refreshment when each memory block is not accessed for a constant period. An internal timer circuit manages a waiting time for the memory block shifting to a nonvolatile mode after entering a non-accessed state. Thus, the semiconductor memory device can attain stable power consumption reduction hardly influenced by a user state.
Claims16
A semiconductor memory device comprising:
- a memory cell array having memory cells, each including a ferroelectric capacitor and an access transistor for accessing said ferroelectric capacitor, arranged in the form of a matrix, said memory cell array being split into a plurality of memory blocks;
- access detection means for detecting that data of each said memory block is accessed from the exterior;
- a plurality of mode set means being provided in correspondence to said plurality of memory blocks respectively, each said mode set means for receiving an output of said access detection means and setting an operation mode of a corresponding memory block at a first mode when a non-accessed period of said corresponding memory block not accessed from the exterior exceeds a prescribed waiting time while setting said operation mode at a second mode when said non-accessed period stays no more than said prescribed waiting time;
- refresh means for stopping data refreshment of each said memory block when said operation mode is said first mode while making data refreshment of said memory block when said operation mode is said second mode;
- and
- mode switching means for switching an operation mode of each said memory block in such a way that said data written in each of said memory cells is held as a remanent polarization quantity of said ferroelectric capacitor during said first mode while said data is held as potential difference between electrodes of each said ferroelectric capacitor during said second mode,
- each said mode set means including timer means for measuring said non-accessed period on the basis of a reference clock.
Dependencies are inferred from the claim text.