Sense amplifier configuration for a 1T/1C ferroelectric memory
AssigneeRamtron International Corporation
InventorsJudith E. Allen, Dennis R. Wilson, Lark E. Lehman
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Abstract
A sense amplifier cell layout for use in a 1T/1C ferroelectric memory array includes a first sense amplifier having two input/output nodes for receiving a first bit line signal and a first inverted bit line signal and a second sense amplifier having two input/output nodes for receiving a second bit line signal and a second inverted bit line signal, wherein the combined width of the first and second sense amplifiers is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
Claims20
A sense amplifier cell for use in a 1T/1C ferroelectric memory array comprising:
- a first sense amplifier having two input/output nodes for receiving a first bit line signal and a first inverted bit line signal;
- and
- a second sense amplifier having two input/output nodes for receiving a second bit line signal and a second inverted bit line signal,
- wherein the combined width of the first and second sense amplifiers is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
A sense amplifier cell for use in a 1T/1C ferroelectric memory array comprising:
- a first sense amplifier section having two input/output nodes for receiving a first bit line signal and a first inverted bit line signal;
- a second sense amplifier section having two input/output nodes for receiving a second bit line signal and a second inverted bit line signal;
- a third sense amplifier section having two input/output nodes for receiving the first bit line signal and the first inverted bit line signal;
- a fourth sense amplifier section having two input/output nodes for receiving the second bit line signal and the second inverted bit line signal,
- wherein the width of the sense amplifiers cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
A row of sense amplifier cells for use in a 1T/1C ferroelectric memory array, each sense amplifier cell comprising:
- a first sense amplifier having two input/output nodes for receiving a first bit line signal and a first inverted bit line signal;
- and
- a second sense amplifier having two input/output nodes for receiving a second bit line signal and a second inverted bit line signal,
- wherein the width of the sense amplifier cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
Dependencies are inferred from the claim text.