Electronic memory device having bit lines with block selector switches

A method of implementing a memory block having a cell matrix configuration for incorporation to a section of a virtual ground integrated memory device, wherein each memory cell is identified by an intersection of a continuous bit line with a word line orthogonal to the bit line, said block being formed on a semiconductor substrate having a first type of conductivity, the method comprising the following steps:

• defining a plurality of active areas isolated from one another by selective growth of a field oxide layer, said active areas being provided in a first region for formation of memory cells and in a second region for formation of address devices and block selectors;
• growing a gate oxide layer;
• masking for removal of the gate oxide layer from the first region of the cells;
• implanting the first region to define a threshold voltage of the memory cells;
• growing a thin layer of tunnel oxide in the first region;
• depositing a ply structure comprising a first conductive layer, an intermediate dielectric layer, and a second conductive layer;
• photolithography processing using a so-called `POLY1` mask to define, in said ply structure, a plurality of parallel strips alternately joined by linking areas located in the second region of the block selectors;
• selectively etching away the second conductive layer, intermediate dielectric layer, first conductive layer, gate and/or tunnel oxide layer, and field oxide layer, if any, and defining continuous bit lines and segments of bit lines whose longitudinal stretch is limited by said linking areas;
• implanting for conferring, on the bit lines, a conductivity type other than a conductivity type of the second conductive layer;
• filling with dielectric the regions exposed for the implantation;
• masking the first region and processing photolithographically to allow of the removal, from the second region, of the second conductive layer and the intermediate dielectric layer;
• masking for implantation in the second region of appropriate circuitry to modify threshold voltages of the address devices and the block selectors;
• depositing a pair of conductive layers as protective and finish layers;
• photolithography processing to define a plurality of word lines by self-aligned etching.

An electronic memory device organized into sections which are in turn divided into blocks, each block of the electronic memory device comprising:

• a plurality of cells connected in a predetermined circuit configuration to form a cell region in the block;
• a decoding circuit connected to the cells;
• an addressing circuit connected to the cells;
• a plurality of parallel conduction lines;
• a plurality of pairs of contact regions placed on opposite sites of the cell region in the block and interconnected by the conduction lines;
• and
• a block selector circuit connected to the block for the purpose of individually selecting a particular block of the electronic memory device, wherein the block selector circuit comprises a plurality of pairs of controlled switches, two switches for each conduction line, each control switch connected between a contact region and a respective conduction line, the controlled switches functioning as a block selector to the electronic memory device.

An electronic memory device, comprising:

• a matrix of memory cells arranged into rows and columns, each memory cell having a conduction terminal and a control terminal;
• a plurality of long bit lines each connecting the conduction terminals of the memory cells of a respective column to each other;
• at least three contact regions that divide the matrix into at least two blocks with each block being coupled between two of the contact regions, each contact region including plural contacts each connected to a respective one of the long bit lines, such that each long bit line interconnects a contact in each of the at least three contact regions;
• and a plurality of block select switches in each long bit line with at least one of the block select switches being positioned in each block for each long bit line, wherein each block select switch selectively provides an interruption in the long bit line in which the block select switch is positioned.