US 5,969,976 A · Division circuit and the division method thereof

Division circuit and the division method thereof

AssigneesHitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System Ltd.

InventorsShumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe

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Abstract

A division method and circuit performs a division for signed data by adding or subtracting a divisor to or from the dividend or the partial remainder from the division, according to the sign of the divisor or the dividend and the partial remainder to acquire a new partial remainder. The division is repeated a predetermined number of times in which a quotient bit is acquired according to the sign of the acquired partial remainder or the divisor. The dividend is corrected by subtracting 1, which is the significance of an LSB of the corresponding dividend, from the dividend when the sign of the dividend is negative, and the corrected dividend is used for the division processing.

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Claims37

Dependent claims

A division circuit for executing a signed division on the basis of repetition of division processings, in which a new partial remainder is achieved by subtracting or adding a divisor from or to a dividend or a partial remainder in accordance with the sign of the dividend or the partial remainder and the sign of the divisor to achieve a new partial remainder and in which a quotient bit is achieved on the basis of the sign of the achieved partial remainder and the sign of the divisor, comprising:

pre-processing means for achieving the sign of the quotient from the sign of the dividend and the sign of the divisor prior to said division processing and for subtracting a value of one having the weight of the LSB of the dividend from said dividend, if said dividend is negative, to correct said dividend thereby to provide a corrected dividend for a target of said division processing;
and
post-processing means for correcting the quotient, which has been achieved by the repetition of said division processing, on the basis of the sign of the quotient.

A division circuit comprising:

a dividend register;
a divisor register;
first control bit storage means;
second control bit storage means;
means for storing the sign of a complement of two, which is stored in said dividend register, in said first control bit storage means;
means for storing the sign of a complement of two, which is stored in said divisor register, in said second control bit storage means;
means for setting a number, which deems the content of said first control bit storage means as the sign bit of said dividend register, to a first dividend and for setting the result, which is obtained by subtracting a value of one having the weight of the LSB of the first dividend from said first dividend, to a second dividend, if said first dividend is negative, and said first dividend to the second dividend if said first dividend is zero or positive;
means for setting the sign of said second dividend to the sign of said first control bit storage means to store said second dividend in said dividend register;
means for setting the number, which deems the content of said first control bit storage means as the sign bit of said dividend register, to the dividend or partial remainder, and for setting a number, which deems the content of said second control bit storage means as the sign bit of said division register, to the divisor, to subtract the divisor from the dividend or the partial remainder, if the signs of said first control bit storage means and said second control bit storage means are identical, and to add the divisor to the dividend or the partial remainder if the signs of said first control bit storage means and said second control bit storage means are different;
means for achieving the sign of the result of said addition/subtraction;
and
means for determining a quotient bit by deciding that the absolute value of the dividend or partial remainder before said addition/subtraction is equal to or more than the absolute value of the divisor, if the sign of said first control bit storage means before said addition/substraction is identical to the sign of said addition/subtraction, and that an absolute value of the dividend or partial remainder before said addition/subtraction is smaller than an absolute value of the divisor, if a sign of said first control bit storage means before said addition/substraction is different from sign of said addition/subtraction.

9 more elements

A division circuit comprising:

a dividend register;
a divisor register;
first control bit storage means;
second control bit storage means;
means for storing a sign of a complement of two, which is stored in said dividend register, in said first control bit storage means;
means for storing a sign of a complement of two, which is stored in said divisor register, in said second control bit storage means;
means for setting a number, which deems the content of said first control bit storage means as a sign bit of said dividend register, to a first dividend and for setting the value, which is prepared by subtracting the sign bit of said first dividend from an LSB of said first dividend, to a second dividend;
means for storing said second dividend in said dividend register by setting a sign of said second dividend to a sign of said first control bit storage means;
third control bit storage means for storing a positive sign, if the signs of said first control bit storage means and said second control bit storage means are identical, and a negative sign if the signs of said first control bit storage means and said second control bit storage means are different;
means for issuing a subtraction command, if the signs of said first control bit storage means and said second control bit storage means are identical, and an addition command if the signs of said first control bit storage means and said second control bit storage means are different;
means for setting a number, which is prepared by shifting a number deeming the content of said first control bit storage means as the sign bit of said dividend register to the more significant side by one bit, to a dividend or partial remainder and for setting a number, which deems the content of said second control bit storage means as the sign bit of said divisor register, to a divisor to add or subtract the divisor to or from the dividend or partial remainder on a basis of said subtraction command or said addition command;
means for storing a sign of the result of said addition/subtraction in said first control bit storage means;
means for storing a result of said addition/subtraction in said dividend register;
means for setting a negation of an exclusive OR between the sign bit of said first control bit storage means and the sign bit of said second control bit storage means to a quotient bit;
quotient storage means for shifting the quotient bit into the LSB;
and
quotient correction means for transforming a quotient expressed in a complement of one into a complement of two after the quotient bit of a predetermined bit number has been determined, if the sign of said third control bit storage means is negative.

14 more elements

Dependencies are inferred from the claim text.

Description36,167 words

Summary3,056 words

#The present invention relates to an architecture of a microcomputer, particularly a RISC (Reduced Instruction Set Computer) type microcomputer and, more particularly, to a technology effective if applied to a microcomputer to be packaged in a device for controlling it.

#Moreover, the present invention relates to a circuit for coded division such as a dividing circuit for a coded binary number of arbitrary length and multi-precision and, more particularly, to a technology effective if applied to a step division of the RISC type microcomputer.

#The most serious bottleneck for reducing the number of machine cycles necessary for executing one instruction is known to be the decoding of the instruction. In order to speed up this decoding, it is now effective to adopt an instruction format of fixed length so that where the boundary of the instruction resides may be informed before a preceding instruction has been interpreted. In the so-called "RISC type computer", most instructions are executed for one cycle by adopting the instruction format of fixed length and a pipe line of multiple steps. The conventional RISC computer has used a 32-bit instruction format without exception. This 32-bit fixed length instruction format is advantageous in that what register is to be read can be determined without decoding the operation code by fixing fields in the instruction formats of a source register and a destination register, and in that no alignment is required when an immediate value is decoded. On the contrary, the 32-bit fixed length instruction format requires 32 bits even when only a simple content of an instruction might be described. As a result, the number of bytes occupied by the instruction code is increased to raise a problem that the ratio of the memory area to be occupied by a program is accordingly increased. If the memory area occupied by the program is increased, a memory having a larger capacity has to be packaged to raise the cost of the microcomputer system, thus making it difficult to construct a system having an excellent performance ratio to the cost. Since the RISC processor is given an architecture for speeding up the executions of instructions by reducing the number of instructions, there arises a tendency that the undefined operation codes grow more for the instruction set. The multiplicity of the undefined operation codes deteriorates the code efficiency of the object program and degrades the memory using efficiency the worse.

Brief description of the drawings90 figures

#FIG. 1 is a block diagram showing one example of a system making use of a microcomputer MCU according to one embodiment of the present invention;

#FIG. 2 is a block diagram showing a microcomputer according to one embodiment of the present invention;

#FIG. 3 is a diagram for conceptionally explaining a pin arrangement for a package of a microcomputer according to the present embodiment;

Detailed description30,717 words

#The present invention will be described in the following in connection with the embodiments thereof in the order of items which are broadly itemized into: a microcomputer adopting an instruction format of fixed length having a smaller bit number than that of the maximum data word length; and coded divisions to be executed by such microcomputer. The contents of the former will be described under Items [1] to [17] whereas the contents of the latter will be described under Items [18] to [24].

#[1] Application System of Microcomputer

#FIG. 1 shows one example of a system which makes use of a microcomputer MCU according to one embodiment of the present invention. This microcomputer MCU is coupled through an external control bus ECB, an external data bus EDB and an external address bus EAB to an external memory EMRY and an external input/output block EI/O defined by the user and is further connected with a port input/output bus PIOB to an external equipment EEQ. This external equipment EEQ is a predetermined device to package the microcomputer system.

Abstract

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Claims37

Description36,167 words

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Classification24 codes

Life of this patent

Description36,167 words