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US 5,969,975 AGranted
Data processing apparatus registers
AssigneeArm Limited
InventorsSimon James Glass, David Vivian Jaggar
Life of this patent
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Abstract
A data processing system is provided including an arithmetic logic unit 20, 22, 24 receiving input operands from M X-bit registers to produce output data words stored within N Y-bit registers, where M/N=3, 8.ltoreq.Y-X.ltoreq.16 and 3X=2Y. This arrangement is particularly suited for digital signal processing and in situations where each input operand is used a plurality of times before a new input operand is loaded in its place in a register.
Claims9
Apparatus for data processing, said apparatus comprising:
- (i) M X-bit registers, where M is a positive integer greater than 1, for receiving respective input operand data words from a data storage device;
- (ii) an arithmetic logic unit for performing arithmetic logic operations upon said input operand data words stored in said X-bit registers to generate output data words;
- (iii) N Y-bit registers, where N is a positive integer greater than 1, for receiving said output data words from said arithmetic logic unit;
- (iv) wherein M/N=3, 8.ltoreq.Y-X <16 and 3X=2Y.
1 more element
Dependencies are inferred from the claim text.