Electrostatic wafer clamp having low particulate contamination of wafers

#This invention relates to apparatus for electrostatic clamping of semiconductor wafers in a vacuum processing chamber and, more particularly, to electrostatic clamping apparatus which provides excellent performance with respect to particulate contamination of wafers. The apparatus is particularly useful in ion implantation systems, but is not limited to such use.

#In the fabrication of integrated circuits, a number of well-established processes involve the application of ion beams to semiconductor wafers in vacuum. These processes include, for example, ion implantation, ion beam milling and reactive ion etching. In each instance, a beam of ions is generated in a source and is directed with varying degrees of acceleration toward a target wafer. Ion implantation has become a standard technique for introducing conductivity-altering impurities into semiconductor wafers. A desired impurity material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy and the ion beam is directed at the surface of the wafer. The energetic ions in the beam penetrate into the bulk of the semiconductor material and are embedded in the crystalline lattice of the semiconductor material to form a region of desired conductivity.

#The target mounting site is a critical part of an ion implantation system. The target mounting site is required to firmly clamp a semiconductor wafer in a fixed position for ion implantation and, in most cases, to provide cooling of the wafer. In addition, means must be provided for exchanging wafers after completion of ion implantation. Cooling of wafers is particularly important in commercial semiconductor processing wherein a major objective is to achieve a high throughput in terms of wafers processed per unit time. One way to achieve high throughput is to use a high current ion beam so that the implantation process is completed in a shorter time. However, large amounts of heat are likely to be generated by the high current ion beam. The heat can result in uncontrolled diffusion of impurities beyond prescribed limits in the wafer and in degradation of patterned photoresist layers. It is usually necessary to provide wafer cooling in order to limit the maximum wafer temperature to about 100.degree. C.

#For a better understanding of the present invention, reference is made to the accompanying drawings, which are incorporated herein by reference and in which:

#FIG. 1 is a schematic plan view of an example of electrostatic wafer clamping apparatus suitable for incorporation of the present invention;

#FIG. 2 is a schematic cross-sectional view of the wafer clamping apparatus, taken along the line 2--2 of FIG. 1;

#An example of apparatus for electrostatic clamping of a workpiece, such as a semiconductor wafer, is shown in simplified form in FIGS. 1-4. An electrostatic wafer clamping apparatus includes a platen 10 and a clamping control circuit 12 for applying clamping voltages to the platen 10 when clamping of a workpiece is desired. The platen 10 includes a support plate, or a platen base 14, and six sector assemblies 20, 22, 24, 26, 28 and 30 mounted on an upper surface of platen base 14. The platen base 14 is generally circular and may have a central opening 18 for a wafer lift mechanism (not shown).

#Each of the sector assemblies includes a sector electrode located between an upper sector insulator and a lower sector insulator. Sector assemblies 20, 22, 24, 26, 28 and 30 include sector electrodes 40, 42, 44, 46, 48 and 50, respectively. Upper sector insulators 60, 62, 64, 66, 68 and 70 cover electrodes 40, 42, 44, 46, 48 and 50, respectively. The electrodes are preferably thin metal layers formed on the lower surfaces of the respective upper sector insulators. The electrodes 40, 42, 44, 46, 48 and 50 preferably have equal areas and are symmetrically disposed with respect to a center 72 of platen 10. The electrodes are electrically isolated from each other and, in a preferred embodiment, are sector-shaped as shown in FIG. 1. The upper surfaces of sector insulators 60, 62, 64, 66, 68 and 70 are coplanar. As discussed below, the upper section insulators preferably have a thin coating which defines a wafer clamping surface 76. When the coating is not utilized, the upper surfaces of the upper sector insulators define the wafer clamping surface. As shown in FIG. 2, sector assembly 20 includes a lower sector insulator 80 and sector assembly 26 includes a lower sector insulator 86. The remaining sector assemblies have the same construction. Preferably, the upper and lower sector insulators of each sector assembly overlap the edges of the respective electrodes to prevent contact between the electrodes and the wafer.

#In the embodiment of FIGS. 1-4, a separate sector assembly including sector-shaped upper and lower sector insulators, is fabricated for each electrode. In other embodiments, the upper insulator or the lower insulator, or both, may be formed as a circular disk. Multiple electrodes may be formed on the lower surface of the circular upper insulator. This configuration may be practical for relatively small platens.