Test circuit for verifying operation of an arc fault detector

Abstract

A test circuit for arc fault detectors of the type which respond to step changes in ac current over time generated each time an arc is struck includes a low frequency relaxation oscillator which generates a repetitive signal with step changes like those produced by an arc fault. The relaxation oscillator includes a capacitor charged through a resistor and shunted by a voltage breakdown device, preferably a diac. The capacitor is rapidly discharged when its voltage reaches the breakdown voltage of the voltage breakdown device to generate the step change which is input to the arc fault detector. With a repetition rate of the relaxation oscillator not greater than about 15 repetitions per second (rps), and preferably about 5 rps, a user can manually determine the time to trip to verify arc fault detector operation. With the oscillator operating at such a low frequency, a signaling device such as a light emitting diode (LED) placed in series with the voltage breakdown device, permits the user to manually count the number of step changes required to produce a trip thereby providing further verification of detector operability.

Dependencies are inferred from the claim text.