DC offset and gain correction for CMOS image sensor

An imaging system providing means for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager, the imaging system comprising:

• (a) memory means for storing a plurality of gain correction coefficients, one for each CDS circuit and a plurality of dc offset correction coefficients, one for each CDS circuit;
• (b) means for determining a reference dc offset value and a reference gain value;
• (c) means for measuring an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output;
• (d) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit;
• (e) means for updating the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit;
• and
• (f) a correction circuit for correcting the output of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattem noise in the row of CDS circuits.

An imaging system, comprising:

• (1) a row of CDS circuits for sampling output signals provided by pixel circuits of an array of pixel sensor circuits;
• and
• (2) a processor coupled to input, output, and control lines of each CDS circuit of the row of CDS circuits, wherein the processor:
• (a) stores a plurality of gain correction coefficients, one for each CDS circuit;
• (b) stores a plurality of dc offset correction coefficients, one for each CDS circuit;
• (c) determines a reference dc offset value and a reference gain value;
• (d) measures an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output;
• (e) compares the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit;
• (f) updates the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit;
• and
• (g) corrects, with a correction circuit, the outut of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattern noise in the row of CDS circuits.

An imaging system comprising:

• (a) a row of CDS circuits;
• (b) memory means for storing a plurality of gain correction coefficients, one for each CDS circuit, and a plurality of dc offset correction coefficients, one for each CDS circuit;
• (c) means for determining a reference dc offset value and a reference gain value;
• (d) means for measuring an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output;
• (e) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit;
• (f) means for updating the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit;
• and
• (g) a correction circuit for correcting the output of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattern noise in the row of CDS circuits.

A method for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager, the method comprising the steps of:

• (a) storing a plurality of gain correction coefficients having an initial value;
• (b) storing a plurality of dc offset correction coefficients having an initial value;
• (c) determining a reference dc offset value and a reference gain value, comprising the steps of:
• (1) applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value;
• and
• (2) applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value;
• (d) determining an actual dc offset value and an actual gain value for each CDS circuit;
• (e) comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively;
• and
• (f) updating the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.

An imaging system providing means for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager, the imaging system comprising:

• (a) memory means for storing a plurality of gain correction coefficients having an initial value and a plurality of dc offset correction coefficients having an initial value;
• (b) means for determining a reference dc offset value and a reference gain value, said means comprising:
• (1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value;
• and
• (2) means for applying a fall well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and for calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value;
• (c) means for determining an actual dc offset value and an actual gain value for each CDS circuit;
• (d) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively;
• and
• (e) means for updating the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.

An imaging system, comprising:

• (1) a row of CDS circuits for sampling output signals provided by pixel circuits of an array of pixel sensor circuits;
• and
• (2) a processor coupled to input, output, and control lines of each CDS circuit of the row of CDS circuits, wherein the processor:
• (a) stores a plurality of gain correction coefficients having an initial value;
• (b) stores a plurality of dc offset correction coefficients having an initial value;
• (c) determines a reference dc offset value and a reference gain value by:
• applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value;
• and
• applying a full well signal to the input of a reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value;
• (d) determines an actual dc offset value and an actual gain value for each CDS circuit;
• (e) compares the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively;
• and
• (f) updates the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.

An imaging system comprising:

• (a) a row of CDS circuits;
• (b) memory means for storing a plurality of gain correction coefficients having an initial value and a plurality of dc offset correction coefficients having an initial value;
• (c) means for determining a reference dc offset value and a reference gain value, said means comprising:
• (1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value;
• and
• (2) means for applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and for calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value;
• (d) means for determining an actual dc offset value and an actual gain value for each CDS circuit;
• (e) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively;
• and
• (f) means for updating the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.