System and method of synchronizing multiple buffers for display

A graphics system for a computer system including a system memory with two memory locations for storing consecutive display lists, the graphics system comprising:

• a frame buffer including a plurality of buffers;
• and
• a graphics processor coupled to said frame buffer and for coupling to the system memory, comprising:
• a buffer switch memory that stores an address, an arm bit and a continue bit;
• display logic that reads said address from said buffer switch memory and that uses said address to retrieve rendered data for display from one of said plurality of buffers;
• and
• rendering logic that retrieves a next display list from the system memory after said continue bit is set, that renders said retrieved display list into another one of said plurality of buffers, that writes an address corresponding to said another one of said plurality of buffers into said buffer switch memory, that clears said continue bit after rendering said retrieved display list, set said arm bit, waiting until said arm bit is cleared, and that sequences through said plurality of buffers to render a plurality of display lists.

A computer system for rendering and displaying a plurality of display lists, comprising:

• a display device;
• a frame buffer including a plurality of buffers;
• a system memory;
• a graphics processor coupled to said frame buffer, said display device and said system memory, said graphics processor comprising:
• a buffer switch memory that stores an address and an arm bit;
• display logic that reads said address from said buffer switch memory and that uses said address to retrieve rendered data for display from one of said plurality of buffers;
• and
• rendering logic that retrieves a next display list from said system memory after a continue indication is provided for said next display list, that renders said retrieved display list into another one of said plurality of buffers, that writes an address corresponding to said another one of said plurality of buffers into said buffer switch memory, that clears said continue indication after rendering said retrieved display list, set said arm bit, waiting until said arm bit is cleared, and that sequences through said plurality of buffers to render the plurality of display lists;
• and
• a central processor that writes display lists into said system memory and that provides a corresponding continue indication after writing each display list.