Drive circuit for a matrix-type display apparatus

A drive circuit for a matrix-type display apparatus, comprising:

• n selection shift registers for outputting selection shift signals in the same number as scanning electrodes by shifting selection data signals having a width of n selection periods (n is an integer of not less than 2) in sync with a clock having a period of n selection periods;
• n erase shift registers for outputting erase shift signals obtained by shifting erase data signals indicative of information different from that of the selection data signals in the same manner as said selection shift registers, the erase data signals having the same width as the selection data signals;
• first logical product output means for obtaining a logical AND of one of n select signals having a constant period for determining a selection voltage application period and the selection shift signals, said first logical AND output means being provided in the same number as the selection shift signals for each pair of the selection shift register and the erase shift register;
• second logical product output means for obtaining a logical AND of one of n blank signals having a constant period for determining an erase voltage application period and the erase shift signals, said second logical product output means being provided in the same number as the erase shift signals for each pair of the selection shift register and the erase shift register;
• first logical sum output means for obtaining a logical OR of logical ANDs obtained from said first logical product output means based on selection shift signals which are in the same order of output respectively from said n selection shift registers;
• and
• second logical sum output means for obtaining a logical OR of logical ANDs obtained from said second logical product output means based on erase shift signals which are in the same order of output respectively from said n erase shift registers,
• wherein the n blank signals are inputted in such a manner that the significant period thereof is not overlapped with that of the n select signals, and the clock, the n select signals and the n blank signals are inputted in phase shifted by one selection period for each pair of the selection shift register and the erase shift register.

A drive circuit for a matrix-type display apparatus, comprising:

• n shift registers for outputting shift signals in the same number as scanning electrodes by shifting data signals containing two kinds of information having a width of an integer multiple of n selection periods (n is an integer of not less than 2) in sync with a clock having a period of the n selection periods;
• first logical product output means for obtaining a logical AND of one of n select signals having a constant period for determining a selection voltage application period, a shift signal and an identification signal for identifying information contained in the data signals, said first logical product output means being provided in the same number as shift signals for each shift register;
• second logical product output means for obtaining a logical product of one of n blank signals having a constant period for determining an erase voltage application period, a shift signal and an identification signal, said second logical product output means being provided in the same number as the shift signals per shift register;
• logical negation input means for negating an input state of the identification signal between said first logical product output means and said second logical product output means against each order, and between respective orders of even number and orders of odd number against each other of said first logical product output means and said second logical product output means;
• first logical sum output means for obtaining a logical OR of logical ANDs obtained from said first logical product output means based on shift signals which are in the same order of output respectively from said n shift registers;
• and
• second logical sum output means for obtaining a logical OR of logical ANDs obtained from said second logical product output means based on the shift signals which are in the same order of output respectively from said n shift registers,
• wherein the clock signal, the select signals and the blank signals are inputted at phase shifted by one selection period for each shift register, while the identification signal is a clock having a period of 2n selection periods when the width of the data signal is `n` multiplied by an even number, while having a period of 3n selection periods when the width of the data signal is `n` multiplied by an odd number.

A drive circuit for a matrix-type display apparatus, comprising:

• selection shift registers for outputting a selection shift signals in the same number as scanning electrodes by shifting a selection data signal having a width of not less than two periods of a clock in sync with the clock;
• first logical product output means for obtaining a logical AND of selection shift signals outputted from three adjoining output terminals of the selection shift registers;
• second logical product output means for obtaining a logical AND of selection shift signals, which are respectively first and second in order of output among three selection shift signals, and a first select signal having a constant period for determining a selection voltage application period when the selection voltage is first applied to a specific one of three adjoining scanning electrodes;
• third logical product output means for obtaining a logical AND of selection shift signals which are respectively second and third in order of output among the three selection shift signals and a second select signal having a constant period for determining a selection voltage application period when applying the selection voltage last to the specific scanning electrode;
• and
• first logical sum output means for obtaining a logical OR of logical ANDs from said first logical product output means, said second logical product output means, and said third logical product output means.