Digital convergence correction device outputting an analog correction signal
AssigneeMatsushida Electric Industrial Co., Ltd.
InventorMasashi Imai
Life of this patent
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Abstract
A digital convergence correction device converts correction data into serial data by using a parallel/serial converter, and further converts the serial data into an analog correction signal by using a serial input type digital/analog converter, and outputs the analog correction signal in order to correct misconvergence.
Claims7
A digital convergence correction device, which outputs an analog correction signal by using digital correction data, comprising:
- a memory for storing multi-channel digital correction data;
- at least one data latch connected to said memory for receiving and temporarily storing a portion of said multi-channel digital correction data received from said memory;
- at least one parallel/serial converter connected to said at least one data latch for converting said multi-channel digital correction data received from said at least one data latch into serial data;
- and
- at least one serial input type digital/analog converter connected with said at least one parallel/serial converter for receiving said serial data and for converting said serial data into said analog correction signal.
A digital convergence correction device, which outputs an analog correction signal by using digital correction data, comprising:
- an 8-bit wide memory for storing 8-bit digital correction data;
- at least one pair of 8-bit wide data latches connected to said 8-bit wide memory for holding a sequence of two of said 8-bit digital correction data received from said 8-bit wide memory;
- and
- at least one 16-bit wide data latch connected to said at least one pair of 8-bit wide data latches for forming 16-bit wide digital correction data from said sequence of two of said 8-bit digital correction data received from said at least one pair of 8-bit data latches.
A digital convergence correction device, which outputs an analog correction signal by using digital correction data, comprising:
- an m-bit wide memory for storing m-bit digital correction data wherein m is a natural number;
- at least one of a quantity of n, m-bit wide data latches connected to said m-bit wide memory for holding a sequence of n of said m-bit digital correction data received from said m-bit wide memory wherein n is a natural number;
- and
- at least one (n.times.m)-bit wide data latch connected to at least one of said quantity of n, m-bit wide data latches for forming (n.times.m)-bit wide digital correction data from said sequence of n of said m-bit digital correction data received from said at least one of said quantity of n, m-bit data latches.
Dependencies are inferred from the claim text.