Quaternary signal encoding

Apparatus having at least one quaternary signal input for receiving a quaternary encoded signal selected from one of a high impedance high level signal, a low impedance high level signal, a high impedance low level signal and a low impedance low level signal, said apparatus comprising an input stage connected to said input, said input stage including:

• an input buffer for sensing a high level signal or a low level signal at said input;
• and
• an output driver for selectively driving said signal input towards a selectable signal level, said output driver being connected to receive an inverted signal level formed by the inverse of a signal level sensed by said input buffer in a first phase of operation for driving said input in a second phase of operation towards said inverse signal level,
• whereby no change in signal level is indicative of said high signal level or said low signal level sensed in said first phase being said low impedance high level signal or said low impedance low level signal, respectively, and a change in signal level is indicative of said high level signal or said low level signal sensed in said first phase being said high impedance low level signal or said low impedance low level signal, respectively.

An integrated circuit comprising a plurality of quaternary signal inputs, each for receiving a quaternary encoded signal selected from one of a high impedance high level signal, a low impedance high level signal, a high impedance low level signal and a low impedance low level signal, said apparatus comprising an input stage connected to said input, said input stage including:

• an input buffer for sensing a high level signal or a low level signal at said input;
• and
• an output driver for selectively driving said signal input towards a selectable signal level, said output driver being connected to receive an inverted signal level formed by the inverse of a signal level sensed by said input buffer in a first phase of operation for driving said input in a second phase of operation towards said inverse signal level,
• whereby no change in signal level is indicative of said high signal level or said low signal level sensed in said first phase being said low impedance high level signal or said low impedance low level signal, respectively, and a change in signal level is indicative of said high level signal or said low level signal sensed in said first phase being said high impedance low level signal or said low impedance low level signal, respectively.

A method of inputting quaternary encoded signals comprising:

• encoding a quaternary encoded signal by selectively generating one of a high impedance high level signal, a low impedance high level signal, a high impedance low level signal and a low impedance low level signal;
• inputting said quaternary encoded signal to a quaternary signal input;
• and
• decoding said quaternary encoded signal by determining whether said signal is a said high impedance high level signal, a said low impedance high level signal, a said high impedance low level signal or a said low impedance low level signal, wherein said decoder step comprises two phases, whereby in a first phase a determination is made as to whether the signal at the input is a high level signal or a low level signal, and in a second phase an inverse drive is applied to said input and a determination is made as to whether the signal level changes, a change in signal level being indicative of a high impedance signal and no change being indicative of a low impedance signal.

A method of inputting quaternary signals to a circuit, said method comprising:

• a) supplying to an input of said circuit an input signal selected from one of four quaternary encoded signals, namely a high impedance high level signal, a low impedance high level signal, a high impedance low level signal and a low impedance low level signal;
• b) detecting a signal level at said input during a first phase;
• c) in a second phase, driving said input towards a signal level opposite to that detected at said input during said first phase;
• and
• d) detecting a signal level at said input during said second phase, no change in signal level with respect to said first phase being indicative of high signal level or low signal level detected in said first phase representing a low impedance high level signal or low impedance low level signal, respectively, and a change in signal level with respect to said first phase being indicative of a high signal level or low signal level detected in said first phase representing a high impedance high level signal or high impedance low level signal, respectively.