Phase locked loop lock condition detector

A circuit, comprising:

• a phase locked loop comprising (i) an oscillator generating an output oscillator signal and (ii) a comparator comparing the oscillator output signal to a reference signal, said comparator generating a control signal for controlling said oscillator;
• and
• a lock condition detector for detecting whether the oscillator output signal is within a prescribed lock condition relative to said reference signal based on the control signal generated by said comparator, said lock condition detector comprising
• a first time integrator including a plurality of stages, said first time integrator sampling the control signal from said comparator and shifting the value of the sampled signal through said plurality of stages at a rate controlled by one of (i) the reference signal and (ii) the oscillator output signal, and
• a logic circuit having inputs coupled to said stages of said integrator, said logic circuit implementing a logic function, associated with the prescribed lock condition, on a plurality of the values of the sampled control signal in said stages and outputting a lock detection signal indicative of the prescribed lock condition having been met.

A method of generating a lock condition signal for a phase locked loop circuit having an oscillator generating an output clock signal and a comparator comparing the output of said oscillator to a reference signal, the comparator generating a control signal for controlling said oscillator, said method comprising the steps of:

• taking a plurality of samples of the control signal at a sampling rate;
• time shifting the plurality of samples at the sampling rate;
• examining the plurality of time shifted samples according to criteria associated with a prescribed lock condition between the reference signal and the output clock signal;
• and
• generating a signal indicative of whether the lock condition criteria is met or not met.