US 5,969,573 A · Amplifier circuit with small offset voltage influence

Abstract

An amplifier circuit influenced less by an offset voltage and capable of permitting an as broad as possible dynamic range is provided. This amplifier circuit includes first and second MOS transistors M1, M2; a first operational amplifier OP1 having an inverting input terminal connected to the drain of the first MOS transistor and a non-inverting input terminal connected to the drain of the second MOS transistor; a second operational amplifier OP2 having two input terminals such that one input terminal is connected to the drain of the second MOS transistor and the other input terminal is connected to a second power supply VD; a first resistance circuit provided between the drain of the first MOS transistor and the output terminal of the first operational amplifier; a second resistance circuit having the same resistance value as that of the first resistance circuit provided between the drain of the second MOS transistor and a third power supply VC; a first load circuit for delivering load current to the drain of the first MOS transistor; and a second load circuit for delivering load current of the same value as the load current to the drain of the second MOS transistor, thus to control load currents flowing in the first and second load circuits by the output of the second operational amplifier so that the drain voltage of the second MOS transistor becomes equal to the second power supply voltage.

Claims18

Dependent claims

A single output differential amplifier circuit comprising:

first and second MOS transistors of a first conductivity type in which their characteristics are substantially the same, their sources being commonly connected to a first power supply;
a first operational amplifier having an inverting input terminal connected to a drain of the first MOS transistor and a non-inverting input terminal connected to a drain of the second MOS transistor;
a second operational amplifier having two input terminals such that one input terminal is connected to the drain of the second MOS transistor and the other input terminal is connected to a second power supply;
a first resistance circuit provided between the drain of the first MOS transistor and an output terminal of the first operational amplifier;
a second resistance circuit having substantially the same resistance value as that of the first resistance circuit provided between the drain of the second MOS transistor and a third power supply;
a first load circuit for delivering a load current to the drain of the first MOS transistor;
and
a second load circuit for delivering a load current of the same value as the load current delivered to the drain of the first MOS transistor to the second MOS transistor,
wherein an output of the second operational amplifier controls the load currents flowing in the first and second load circuits so that a drain voltage of the second MOS transistor becomes equal to a voltage of the second power supply.

6 more elements

A full differential amplifier circuit comprising:

first and second MOS transistors of a first conductivity type in which their characteristics are substantially the same, their sources being commonly connected to a first power supply;
a first operational amplifier having an inverting input terminal connected to a drain of the first MOS transistor and a non-inverting input terminal connected to a drain of the second MOS transistor,
a second operational amplifier having an inverting input terminal connected to the drain of the second MOS transistor and a non-inverting input terminal connected to a second power supply,
a first resistance circuit provided between the drain of the first MOS transistor and an output terminal of the first operational amplifier,
a second resistance circuit having substantially the same resistance value as that of the first resistance circuit provided between the drain of the second MOS transistor and an output terminal of the second operational amplifier,
a first load circuit connected to the drain of the first MOS transistor to deliver load current to the drain of the first MOS transistor, and
a second load circuit connected to the drain of the second MOS transistor to deliver load current equal to the load current delivered to the drain of the first MOS transistor to the second MOS transistor,
wherein outputs of the first and second operational amplifiers are differential outputs and control load currents flowing in the first and second load circuits.

5 more elements

Dependencies are inferred from the claim text.

Amplifier circuit with small offset voltage influence

Life of this patent

Amplifier circuit with small offset voltage influence

Life of this patent

Abstract

Claims18