Input and output circuit with wide voltage tolerance

An input and output (I/O) circuit with wide voltage tolerance, the I/O circuit comprising:

• an output pad for receiving a first voltage;
• a feedback circuit coupled to the output pad;
• a first NMOS transistor, wherein a gate of the first NMOS transistor is for receiving a second voltage;
• a first PMOS transistor, wherein a gate of the first PMOS transistor is coupled to the feedback circuit, and the first PMOS transistor is coupled together with the first NMOS transistor in parallel to form a first transmission gate, in which a first I/O terminal of the first transmission gate is coupled to the output pad and a second I/O terminal of the first transmission gate is for outputting a third voltage;
• a second PMOS transistor, wherein a source of the second PMOS transistor receives the second voltage, and the drain of the second PMOS transistor is coupled to the second I/O terminal of the first transmission gate;
• a second NMOS transistor, wherein a source of the second NMOS transistor is coupled to the drain of the second PMOS transistor and the second I/O terminal of the first transmission gate, and the drain of the second NMOS transistor is grounded;
• when the I/O circuit is at an output mode and either of the second PMOS transistor or the second NMOS transistor is "on", the feedback circuit is grounded and causes the output pad at full swing;
• when the I/O circuit is at high impedance, both the second PMOS transistor and the second NMOS transistor are "off", and when the first voltage is smaller than the second voltage, the third voltage can track the first voltage through the first NMOS transistor until the third voltage is equal to V.sub.2nd -V.sub.t-first-NMOS, where V.sub.2nd is the second voltage and V.sub.t-first-NMOS is the threshold voltage of the first NMOS transistor;
• and
• when the I/O circuit is at high impedance, both the second PMOS transistor and the second NMOS transistor being "off", and when the first voltage is smaller than the second voltage, the first PMOS is turned off by the feedback circuit, in which the third voltage is kept at the quantity of V.sub.2nd -V.sub.t-first-NMOS under the control of the first NMOS transistor.