Pulse width forming circuit

A pulse width forming circuit, comprising:

• a first delay element for receiving an input pulse and delaying said input pulse by a first delay time;
• an OR gate for receiving said input pulse at an input terminal and a first delayed pulse signal from said first delay element at another input terminal and adding said first delay time to a pulse width of said input pulse;
• a second delay element for receiving an output pulse of said summing means and delaying said output pulse by a second delay time;
• and
• an AND gate for receiving said input pulse and a second delayed pulse signal from said second delay element for producing a pulse waveform having a predetermined pulse width whose starting edge corresponds to an end timing of said input pulse and whose stop edge corresponds to an end timing of said second delayed pulse signal.

A pulse width forming circuit, comprising:

• a plurality of pulse width integration circuits connected in series, each of said pulse width integration circuits comprising;
• a delay element for delaying an incoming pulse by a predetermined delay time;
• summing means for receiving said incoming pulse and a delayed pulse signal from said delay element and adding said delay time to a pulse width of said incoming pulse;
• wherein an input pulse is received by a first stage of said plurality of pulse width integration circuits as said incoming pulse and an overall delayed pulse is produced at an output of a last stage of said plurality of pulse width integration circuits;
• and
• gate means for receiving said input pulse and said overall delayed pulse for producing a pulse waveform having a predetermined pulse width whose starting edge corresponds to an end timing of said input pulse and whose stop edge corresponds to an end timing of said overall delayed pulse.

A pulse width forming circuit, comprising:

• a plurality of pulse width integration circuits connected in series, each of said pulse width integration circuits comprising;
• a delay element for delaying an incoming pulse by a predetermined delay time;
• an OR gate for receiving said incoming pulse and a delayed pulse signal from said delay element and adding said delay time to a pulse width of said incoming pulse;
• wherein an input pulse is received by a first stage of said plurality of pulse width integration circuits as said incoming pulse and an overall delayed pulse is produced at an output of a last stage of said plurality of pulse width integration circuits;
• and
• an AND gate for receiving said input pulse and said overall delayed pulse for producing a pulse waveform having a predetermined pulse width whose starting edge corresponds to an end timing of said input pulse and whose stop edge corresponds to an end timing of said overall delayed pulse.

A pulse width forming circuit, comprising:

• a delay element for receiving an input pulse and delaying said input pulse by a predetermined delay time;
• an OR gate for receiving said input pulse at an input terminal and a delayed pulse signal from said delay element at another input terminal and for adding said delay time to a pulse width of said input pulse;
• and
• an AND gate for receiving said input pulse and an output pulse of said OR gate for producing a pulse waveform having a predetermined pulse width whose starting edge corresponds to an end timing of said input pulse and whose stop edge corresponds to an end timing of said output pulse of said OR gate.