Digital delay circuit and digital PLL circuit with first and second delay units
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsToshio Kishi, Yukihiko Shimazu
Life of this patent
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Abstract
A digital delay circuit and a digital PLL circuit achieve reduction in size and power consumption. Each of a first delay line (301) and a second delay line (302) includes a plurality of delay elements. A control circuit (200) selects the delay element(s) included in a delay line (300), and a second clock signal (S11) passes only through the selected delay element(s). That is, the second clock signal (S11) does not pass through the non-selected delay element(s), which reduces power consumption.
Claims10
A digital delay circuit comprising:
- a control circuit receiving a digital signal which changes an amount of delay, and for taking a count in accordance with said digital signal to output a count value;
- and
- a delay line receiving a delay object signal and said count value, and comprising
- a first delay line including a plurality of first delay portions each having a first delay unit, and
- a second delay line including a plurality of second delay portions each having a second delay unit corresponding to a predetermined number of said first delay units,
- wherein said delay line passes said delay object signal through said first delay portions the number of which is indicated by a lower digit of said count value and through said second delay portions the number of which is indicated by an upper digit of said count value, to output said delay object signal, and
- wherein said delay line includes a potential fixing portion for fixing an input potential of only said first and second delay portions through which said delay object signal does not pass.
A digital PLL circuit receiving a first clock signal, and for generating a second clock signal which follows the phase of said first clock signal,
- said digital PLL circuit comprising:
- a digital delay circuit;
- and
- a phase compare portion receiving said first and second clock signals, and for making a phase comparison between said first and second clock signals to output the compared result as a digital signal which changes the amount of delay,
- said digital delay circuit comprising:
- a control circuit receiving said digital signal, and for taking a count in accordance with said digital signal to output a count value;
- and
- a delay line receiving a delay object signal and said count value, and comprising
- a first delay line including a plurality of first delay portions each having a first delay unit, and
- a second delay line including a plurality of second delay portions each having a second delay unit corresponding to a predetermined number of said first delay units,
- wherein said delay line passes said delay object signal through said first delay portions the number of which is indicated by a lower digit of said count value and through said second delay portions the number of which is indicated by an upper digit of said count value, to output said delay object signal;
- and
- wherein said delay object signal is said second clock signal and said delay object signal outputted by said delay line is inputted as said second clock signal to said delay line.
Dependencies are inferred from the claim text.