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US 5,969,551 AGranted
Clock generator having DLL and semiconductor device having clock generator
AssigneeFujitsu Limited
InventorShinya Fujioka
Life of this patent
Estimating the term…
Abstract
A clock generator including a DLL occupying a small area and a semiconductor device including the clock generator have been disclosed. In the clock generator for generating a plurality of clocks optimally adjusted in phase for a plurality of objects on the basis of a received clock, the DLL is structured hierarchically. A first DLL of a parent level is used in common and second DLLs of child levels are associated with input signals.
Claims18
A clock generator for generating a plurality of clocks adjusted in phase for a plurality of objects in response to a received clock, comprising:
- a first DLL for adjusting a phase of the received clock by delaying the received clock and outputting a coarsely-adjusted clock;
- and
- a plurality of second DLLs, associated with the plurality of objects, for adjusting a phase of the coarsely-adjusted clock by delaying the coarsely-adjusted clock and outputting the plurality of clocks,
- wherein said first DLL judges whether a phase difference between a phase of one of the plurality of clocks and a predetermined optimal phase value is within a predetermined range of phase differences;
- and if the phase difference does not fall within the predetermined range of phase differences, said first DLL judges whether the clock is leading or lagging, and changes a magnitude of delay of one of the plurality of clocks in response to the judgement;
- and
- wherein said second DLLs judge whether the plurality of clocks are leading or lagging with respect to the predetermined optimal phase value, and change magnitudes of delay of one of the plurality of clocks in response to the results of the judgement.
4 more elements
A semiconductor device, comprising:
- a clock distribution circuit for distributing an internal clock generated on the basis of an externally input received clock;
- and
- local clock generators for generating a plurality of local clocks generated on the basis of the internal clock supplied from said clock distribution circuit,
- wherein each of said local clock generators comprises:
- a first DLL for adjusting a phase of the internal clock by adjusting a magnitude of delay, by which the internal clock is delayed, stepwise, and outputting a coarsely-adjusted clock;
- and
- a plurality of second DLLs for adjusting a phase of the coarsely-adjusted clock by adjusting the magnitude of delay, by which the coarsely-adjusted clock is delayed, stepwise, and outputting the plurality of local clocks,
- wherein said first DLL judges whether a phase difference between a phase of at least one of the plurality of local clocks and a predetermined optimal clock phase falls within a given range of phase differences;
- and if the phase difference does not fall within the given range of phase differences, said first DLL judges whether the local clock is leading or lagging with respect to the optimal clock phase and changes the magnitude of phase adjustment of one of the plurality of local clocks on the basis of the result of judgement;
- and
- wherein said second DLLs judge whether the plurality of clocks are leading or lagging with respect to the optimal clock phase, and change magnitudes of phase adjustment of one of the plurality of local clocks on the basis of the result of the judgement.
8 more elements
A semiconductor device, comprising:
- a first latch circuit receiving a first input signal in response to a first internal clock;
- a second latch circuit receiving a second input signal in response to a second internal clock;
- a clock buffer circuit receiving an external clock, and outputting said first and second internal clocks;
- the clock buffer circuit including a main DLL circuit receiving said external clock having a coarse accuracy, and outputting a reference clock;
- a first sub DLL circuit receiving the reference clock, associated with said first latch circuit, having a fine accuracy, and outputting said first internal clock;
- a second sub DLL circuit receiving the reference clock, associated with said second latch circuit, having the fine accuracy, and outputting said second internal clock.
3 more elements
Dependencies are inferred from the claim text.