Method and apparatus for mutual synchronization of ASIC devices

Abstract

A method and apparatus are provided for synchronizing communications between different integrated circuits having different individual clock rates. In accordance with exemplary embodiments of the invention, a common clock signal is provided having a frequency greater than or equal to the highest individual clock rate, and the common clock signal is divided to obtain individual clock signals for the different integrated circuits For each integrated circuit an arrangement including a switching device and an edge-triggered storage member is also provided. The arrangement has an input for receiving signals, for example from the other integrated circuits. The arrangement also has an output connected to an input of the integrated circuit. The common clock signal and the individual clock signal corresponding to the integrated circuit are provided to the arrangement. The switching device in the arrangement alternately connects an input of the edge-triggered storage member to one of the arrangement input and the arrangement output, based on a state of the individual clock signal. An output of the edge-triggered storage member functions as the arrangement output. The common clock signal is provided to an edge trigger of the storage member so that on an edge of the common clock signal, the storage member will store a signal present at the storage member input and then provide the currently stored signal at the storage member output.

Dependencies are inferred from the claim text.