US 5,969,542 AGranted

High speed gate oxide protected level shifter

AssigneeAdvanced Micro Devices, Inc.

InventorsReading Maley, Albrecht Schoy

Life of this patent

Estimating the term…

Abstract

An improved gate oxide protected level shifter is provided which has a higher speed of operation than is traditionally available. The level shifter includes a first capacitor coupled between a first output terminal and the input of an inverter and a second capacitor coupled between a first node and the output of the inverter. As a result, the speed of the transitions at the gates of the pair of cross-coupled P-channel MOS transistors is increased several times.

Claims9

Dependent claims

A high speed gate oxide protected level shifter comprising:

an input node for receiving an input signal having first and second levels;
a first output terminal for providing an upper non-inverting output signal having third and fourth levels;
a second output terminal for providing a lower non-inverting output signal having fifth and sixth levels;
a first I/O buffer power supply voltage having an upper voltage level;
a second I/O buffer power supply voltage having a lower voltage level;
a pair of first and second P-channel MOS transistors, said first MOS transistor having its source electrode connected to said first I/O power supply voltage, its drain electrode connected to the gate of said second MOS transistor at a first node, and its gate connected to said first output terminal, said second MOS transistor having its source electrode also connected to said first I/O power supply voltage and its drain electrode also connected to said first output terminal and to the gate of said first MOS transistor;
a pair of third and fourth N-channel MOS transistors, said third MOS transistor having its drain electrode connected to a second node, its source electrode connected to said second power supply voltage, and its gate connected to said input node, said fourth MOS transistor having its drain electrode connected to said second output terminal and its source electrode also connected to said second power supply voltage;
an inverter having its input connected to said input node and its output connected to the gate of said fourth MOS transistor;
fifth and sixth MOS transistors having their conduction path electrodes connected in series and between said first node and said second node, said fifth MOS transistor having its gate connected to a first reference voltage and said sixth MOS transistor having its gate connected to a second reference voltage;
seventh and eighth MOS transistors having their conduction path electrodes connected in series and between said first output terminal and said second output terminal, said seventh MOS transistor having its gate connected to the first reference voltage and said eighth MOS transistor having its gate connected to the second reference voltage;
a first capacitor coupled between the first output terminal and the input of said inverter to quickly turn off said first MOS transistor when said input signal makes a low-to-high transition;
and
a second capacitor coupled between the first node and the output of said inverter to quickly turn off said second MOS transistor when said input signal makes a high-to-low transition.

10 more elements

Dependencies are inferred from the claim text.

patentgrep

Loading patent…

Abstract

A high speed gate oxide protected level shifter comprising:

an input node for receiving an input signal having first and second levels;
a first output terminal for providing an upper non-inverting output signal having third and fourth levels;
a second output terminal for providing a lower non-inverting output signal having fifth and sixth levels;
a first I/O buffer power supply voltage having an upper voltage level;
a second I/O buffer power supply voltage having a lower voltage level;
a pair of first and second P-channel MOS transistors, said first MOS transistor having its source electrode connected to said first I/O power supply voltage, its drain electrode connected to the gate of said second MOS transistor at a first node, and its gate connected to said first output terminal, said second MOS transistor having its source electrode also connected to said first I/O power supply voltage and its drain electrode also connected to said first output terminal and to the gate of said first MOS transistor;
a pair of third and fourth N-channel MOS transistors, said third MOS transistor having its drain electrode connected to a second node, its source electrode connected to said second power supply voltage, and its gate connected to said input node, said fourth MOS transistor having its drain electrode connected to said second output terminal and its source electrode also connected to said second power supply voltage;
an inverter having its input connected to said input node and its output connected to the gate of said fourth MOS transistor;
fifth and sixth MOS transistors having their conduction path electrodes connected in series and between said first node and said second node, said fifth MOS transistor having its gate connected to a first reference voltage and said sixth MOS transistor having its gate connected to a second reference voltage;
seventh and eighth MOS transistors having their conduction path electrodes connected in series and between said first output terminal and said second output terminal, said seventh MOS transistor having its gate connected to the first reference voltage and said eighth MOS transistor having its gate connected to the second reference voltage;
a first capacitor coupled between the first output terminal and the input of said inverter to quickly turn off said first MOS transistor when said input signal makes a low-to-high transition;
and
a second capacitor coupled between the first node and the output of said inverter to quickly turn off said second MOS transistor when said input signal makes a high-to-low transition.

10 more elements