Current inhibiting I/O buffer having a 5 volt tolerant input and method of inhibiting current

A tri-state I/O buffer arranged to be powered by a supply voltage and to drive an output terminal, the output terminal being arranged to receive an external voltage which is higher than the supply voltage during a high impedance, the I/O buffer comprising:

• output driving means connected to the supply voltage and the output terminal for driving the output terminal, said output driving means comprising a first plurality of transistors having a first conductivity type and defining an isolated floating well circuit for operatively connecting the output terminal to the supply voltage and a second plurality of transistors having a second conductivity type and defining a pull-down circuit of the output driving means for operatively connecting the output terminal to ground;
• input controlling means connected to the isolated floating well circuit, the pull-down circuit, and the supply voltage, and arranged for receiving a buffer input signal for controlling the buffer input signal respectively to each of the isolated floating well and pull-down circuits;
• bias controlling means connected to the isolated floating well circuit of said output driving means, connected to the supply voltage, and arranged to receive a tri-state enabling signal and the buffer input signal for controlling a biasing signal to the isolated floating well circuit;
• and
• input isolating means responsive to said input controlling means, connected to the isolated floating well circuit of said output driving means, connected to the supply voltage, and arranged to receive the tri-state enabling signal for operatively isolating an input control signal to the isolated floating well circuit.

A tri-state I/O buffer arranged to be powered by a supply voltage and to drive an output terminal, the I/O buffer comprising:

• output driving means connected to the supply voltage and the output terminal for driving the output terminal, said output driving means including a plurality of transistors defining an isolated floating well circuit for operatively connecting the output terminal to the supply voltage;
• input controlling means connected to said output driving means and the supply voltage, and arranged for receiving a buffer input signal for controlling the buffer input signal to said output driving means;
• input isolating means connected to said isolated floating well circuit and responsive to said input controlling means for operatively isolating an input control signal to the isolated floating well circuit;
• and
• bias controlling means connected to the isolated floating well circuit of said output driving means for controlling a biasing signal to the isolated floating well circuit, said bias controlling means including voltage swing limiting means connected to the isolated floating well circuit for limiting the voltage swing of at least one of the plurality of transistors of the floating well circuit to thereby inhibit overstressing of the gate oxide of the one of the plurality of transistors.

A method of inhibiting current during a high impedance in a tri-state I/O buffer arranged to be powered by a supply voltage and to drive an output terminal, the output terminal being arranged to receive an external voltage which can be higher than the supply voltage during the high impedance, the method comprising:

• operatively connecting the output terminal to the supply voltage with an isolated floating well circuit so as to drive the output terminal;
• controlling a buffer input signal supplied to the isolated floating well circuit;
• controlling a biasing signal to the isolated floating well circuit;
• operatively isolating the controlled buffer input signal being supplied to the isolated floating well circuit:
• and
• limiting the voltage swing of at least one of a plurality of transistors of the floating well circuit to thereby inhibit overstressing of the gate oxide of the at least one of the plurality of transistors when at least one of the plurality of transistors is forwardly biased and the floating well is positively biased by the external voltage applied to the output terminal.