Product term exporting mechanism and method improvement in an EPLD having high speed product term allocation structure

A macrocell which connects between logic forming circuitry of a programmable logic device and an output terminal of the programmable logic device, the macrocell comprising:

• one or more input lines which receive a corresponding one or more logic signals;
• a local logic gate;
• an export logic gate;
• one or more distribution circuits, each distribution circuit connected to a corresponding one of the input lines, wherein each distribution circuit is independently programmable to route a corresponding logic signal to either the local logic gate or the export logic gate;
• a first cascade control circuit connected to both an output terminal of the export logic gate and an output of the local logic gate, wherein the first cascade control circuit is programmable to route logic signals output by the export logic gate to either a second macrocell or a third macrocell and to route logic signals output by the local logic gate to either the third macrocell or the second macrocell, respectively;
• a second cascade control circuit connected to receive logic signals from the second macrocell, wherein the second cascade control circuit is programmable to route logic signals received from the second macrocell to an input of either the export logic gate or the local logic gate;
• and
• a third cascade control circuit connected to receive logic signals from the third macrocell, wherein the third cascade control circuit is programmable to route logic signals received from the third macrocell to an input of either the export logic gate or the local logic gate.

A method of routing logic signals from logic forming circuitry of a programmable logic device to output terminals of the programmable logic device, the method comprising the steps of:

• providing a plurality of first logic signals to a first macrocell of the programmable logic device;
• selecting first and second groups of the first logic signals, wherein the number of first logic signals in the first and second groups can be varied;
• transmitting the first group of the first logic signals to an output terminal corresponding to the first macrocell;
• transmitting either the first group of the first logic signals or the second group of the first logic signals to a second macrocell of the programmable logic device;
• providing a plurality of second logic signals from a third macrocell to the first macrocell;
• and
• selectively transmitting the second logic signals to the output terminal of the first macrocell or to the second macrocell, wherein the first group of the first logic signals includes any number from zero to all of the first logic signals.

A method of routing logic signals from logic forming circuitry of a programmable logic device to output terminals of the programmable logic device, the method comprising the steps of:

• providing a plurality of logic signals to a first macrocell of the programmable logic device;
• selecting a first group and a second group of the logic signals, wherein the number of logic signals in the first group and second group can be varied;
• transmitting the first group to an output terminal corresponding to the first macrocell;
• and
• transmitting either the first group or the second group to a second macrocell of the programmable logic device through one or more intermediate macrocells of the programmable logic device.

A first macrocell which connects between logic forming circuitry of a programmable logic device and an output terminal of the programmable logic device, the first macrocell comprising:

• one or more input lines which are connected to receive a corresponding number of logic signals from the logic forming circuitry;
• a first cascade control circuit for receiving a plurality of logic signals and being programmable to a first state in which the received plurality of logic signals are routed to a second macrocell or a second state in which the received plurality of logic signals are routed to a third macrocell;
• one or more distribution circuits, each distribution circuit coupled to one of the input lines, wherein each distribution circuit is independently programmable to a first state or a second state, wherein a distribution circuit programmed in the first state routes a first set of received logic signals to the output terminal of the programmable logic device and simultaneously to the first cascade control circuit, and wherein a distribution circuit programmed in the second state routes a second group of received logic signals only to the first cascade control circuit;
• and
• a second cascade control circuit having an input terminal coupled to a third macrocell, the second cascade control circuit being programmable to a first state in which output signals from the third macrocell are routed to the output terminal of the programmable logic device or a second state in which the output signals from the third macrocell are routed to the first cascade control circuit.

A first macrocell which connects between logic forming circuitry of a programmable logic device and an output terminal of the programmable logic device, the first macrocell comprising:

• a first cascade control circuit for receiving a plurality of logic signals and routing the plurality of logic signals to a second macrocell;
• one or more input lines which are connected to receive a corresponding number of logic signals from the logic forming circuitry;
• one or more distribution circuits, each distribution circuit coupled to one of the input lines, wherein each distribution circuit is independently programmable to a first state or a second state, wherein a distribution circuit programmed in the first state routes a first set of received logic signals to the output terminal of the programmable logic device and simultaneously to the first cascade control circuit, and wherein a distribution circuit programmed in the second state routes a second group of received logic signals only to the first cascade control circuit;
• and
• a second cascade control circuit having an input terminal coupled to a third macrocell, the second cascade control circuit being programmable to a first state in which output signals from the third macrocell are routed to the output terminal of the programmable logic device or a second state in which the output signals from the third macrocell are routed to the first cascade control circuit.