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US 5,969,538 AGranted
Semiconductor wafer with interconnect between dies for testing and a process of testing
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
Integrated circuit die on a wafer are tested individually, without probing any of the die, using die resident circuitry and connections to selectively provide either a bypass mode wherein the die has direct pad-to-pad connectivity or a functional mode wherein the die has pad to functional core logic connectivity. The die framework further provides a fault tolerant circuit to select a die on a wafer to be placed in functional mode while other die remain in bypass mode.
Claims3
A semiconductor wafer comprising:
- A. a plurality of integrated circuit dies forming a portion of the wafer and being free of any other supporting substrate, each die including functional circuitry for performing normal operating functions and test circuitry for performing testing of the die, each die including plural bond pads coupled to the functional circuitry and test circuitry, each die including a first, second and third bond pad coupled to the test circuitry, each first bond pad adapted receive a control signal and each second bond pad adapted to receive a test signal, the test circuitry being responsive to the control signal selectively to conduct the test signal received at the second bond pad to a third bond pad along one of a test path through the functional circuitry and a bypass path that is isolated from the functional circuitry;
- B. scribe lanes between the die that will be scribed and broken to separate the die from one another;
- and
- C. electrical leads extending across the scribe lanes from die to die and connecting adjacent bond pads on adjacent die, including at least one lead connecting a third bond pad of one die and a second bond pad of an adjacent die.
1 more element
Dependencies are inferred from the claim text.