Back to results
US 5,969,425 AGranted
Borderless vias with CVD barrier layer
AssigneeAdvanced Micro Devices, Inc.
InventorsRobert C. Chen, David C. Greenlaw, John A. Iacoponi
Life of this patent
Estimating the term…
Abstract
Borderless vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an undercut, etched side surface of a lower metal feature. A metal, such as tungsten, is subsequently deposited to fill the borderless via. Embodiments include thermal decomposition of an organic-titanium compound, such as tetrakis-dimethylamino titanium, and treating the deposited titanium nitride in an H.sub.2 /N.sub.2 plasma to lower its resistivity.
Claims15
A semiconductor device comprising:
- a first dielectric layer formed on a substrate;
- a first patterned metal layer having gaps formed on the first dielectric layer, wherein the first patterned metal layer comprises a first metal feature with an upper surface and side surfaces;
- a second dielectric layer formed on the first patterned metal layer;
- a through-hole having an internal surface formed in the second dielectric layer exposing a portion of the upper surface and a portion of a side surface of the first metal feature, wherein the exposed side surface has an undercut concave portion formed by etching the through-hole;
- a layer of chemical vapor deposited barrier material lining the internal surface of the through-hole, the exposed portion of the upper surface and undercut concave portion of the side surface of the first metal feature;
- and
- conductive material in the lined opening filling the through-hole and forming a borderless via.
4 more elements
Dependencies are inferred from the claim text.