Chip package device mountable on a mother board in whichever of facedown and wire bonding manners
AssigneeNEC Corporation
InventorsKoji Yamashita, Yasunori Tanaka, Eiji Hagimoto
Life of this patent
Estimating the term…
Loading patent…
AssigneeNEC Corporation
InventorsKoji Yamashita, Yasunori Tanaka, Eiji Hagimoto
Estimating the term…
A chip package device comprises on its outside surface a plurality of wire bonding electrodes adjacent a plurality of facedown electrodes. The chip package device comprises an IC chip having a plurality of chip electrodes on its face surface and a contact sheet having an inside surface on the face surface and comprising on the outside surface a plurality of conductor patterns which comprises portions extending through the contact sheet to the chip electrodes, respectively, and defines the facedown and the wire bonding electrodes. Such chip package devices can be mounted on a printed circuit board in whichever of a facedown and a wire bonding manner when primary and secondary pads are formed on the board for mechanical and electrical connection to the facedown electrodes, respectively, and for electric connection by bonding wires to the wire bonding electrodes, respectively.
A chip package device comprising an IC chip and a contact sheet having an outside surface and a plurality of facedown electrodes on said outside surface to enclose said IC chip and to provide electric connections to said IC chip, further comprising a plurality of wire bonding electrodes electrically connected on said outside surface to said facedown electrodes, respectively, said IC chip having a chip surface and a plurality of chip electrodes on said chip surface, said contact sheet having an inside surface, wherein said contact sheet comprises on said inside surface a plurality of support pads electrically connected to said facedown electrodes through said contact sheet, respectively, said chip electrodes being electrically connected to said support electrodes, respectively, wherein said facedown electrodes are arranged in a matrix array, said wire bonding electrodes being positioned in a sheet area substantially equal to said chip surface and connected through said contact sheet to said support pads, respectively.
A chip package device comprising an IC chip and a contact sheet having an outside surface and a plurality of facedown electrodes on said outside surface to enclose said IC chip and to provide electric connections to said IC chip, further comprising a plurality of wire bonding electrodes electrically connected on said outside surface to said facedown electrodes, respectively, said IC chip having a chip surface and a plurality of chip electrodes on said chip surface, wherein said contact sheet has an inside surface attached to said chip surface and comprises a plurality of conductor patterns corresponding on said outside surface to said chip electrodes, said conductor patterns having portions extended through said contact sheet to reach said chip electrodes, respectively, each of said conductor patterns providing a corresponding one of said facedown electrodes and a corresponding one of said wire bonding electrodes, wherein said inside surface has an area identical with said chip surface, said wire bonding electrodes being positioned along a periphery of said inside surface.
A chip package device comprising an IC chip and a contact sheet having an outside surface and a plurality of facedown electrodes on said outside surface to enclose said IC chip and to provide electric connections to said IC chip, further comprising a plurality of wire bonding electrodes electrically connected on said outside surface to said facedown electrodes, respectively, said IC chip having a chip surface and a plurality of chip electrodes on said chip surface, wherein said contact sheet has an inside surface attached to said chip surface and comprises a plurality of conductor patterns corresponding on said outside surface to said chip electrodes, said conductor patterns having portions extended through said contact sheet to reach said chip electrodes, respectively, each of said conductor patterns providing a corresponding one of said facedown electrodes and a corresponding one of said wire bonding electrodes, wherein said inside surface has a greater area than said chip surface, said wire bonding pads being positioned along a periphery of said inside surface.
Dependencies are inferred from the claim text.