Back to results
US 5,969,393 AGranted
Semiconductor device and method of manufacture of the same
AssigneeKabushiki Kaisha Toshiba
InventorMitsuhiro Noguchi
Life of this patent
Estimating the term…
Abstract
A semiconductor device comprises a semiconductor substrate having a major surface, a semiconductor region defined between at least two trenches formed in the major surface, a first insulating layer formed on at least side walls of each of the trenches, and a second insulating layer formed in a predetermined area of the surface of the semiconductor region to contact the first insulating layer. The thickness of the first insulating layer at the top of the side walls is set larger than the thickness of the second insulating layer.
Claims21
A semiconductor device comprising:
- a semiconductor substrate having a major surface;
- a semiconductor region defined in said major surface and located between two trenches formed in said major surface;
- a first insulating layer formed adjacent to and along side walls of said trenches;
- a second insulating layer formed on an upper surface of said semiconductor region and upper regions of said side walls of said trenches, which correspond to upper regions of side walls of said semiconductor region, said second insulating layer contacting said first insulating layer on said upper regions of said side walls of said trenches;
- and
- a fourth insulating layer formed between said first insulating layer and said side walls of said trenches, an upper end portion of said fourth insulating layer being butt-joined to said second insulating layer,
- an upper end portion of said first insulating layer being formed in contact and along said second insulating layer where said second insulating layer is formed on said upper regions of said side walls of said trenches, so as to sandwich said second insulating layer between the first insulating layer and said side walls of said trenches.
4 more elements
A semiconductor device comprising:
- a semiconductor substrate having a major surface;
- a semiconductor region defined in said major surface and located between two trenches formed in said major surface;
- a first insulating layer formed adjacent to and along side walls of said trenches;
- a second insulating layer formed on an upper surface of said semiconductor region and upper regions of said side walls of said trenches, which correspond to upper regions of side walls of said semiconductor region, said second insulating layer contacting said first insulating layer on said upper regions of said side walls of said trenches;
- a third insulating layer embedded in each of said trenches with said first insulating layer interposed between said third insulating layer and said side walls of said trenches, such that an upper surface of said third insulating layer is set lower than said major surface of said semiconductor substrate;
- and
- a fourth insulating layer formed between said first insulating layer and said side walls of said trenches, an upper end portion of said fourth insulating layer being butt-joined to said second insulating layer,
- said first insulating layer extending to at least a same plane as said major surface of said semiconductor substrate along said side walls of said trenches, so as to sandwich said second insulating layer between the first insulating layer and said side walls of said trench, and a distance between said first insulating layer and said side walls being set less than a thickness of a portion of said second insulating layer which is formed on said major surface of said semiconductor substrate.
5 more elements
A semiconductor device comprising:
- an insulative base layer having a trench in a major surface thereof;
- a first insulating layer formed adjacent to and along at least corresponding one of upper regions of side walls of said trench;
- a semiconductor region embedded in said trench with said first insulating layer interposed between said semiconductor region and said at least said upper regions of said side walls of said trench;
- and
- a second insulating layer formed at least on an upper surface of said semiconductor region, said second insulating layer contacting said first insulating layer,
- said first insulating layer extending to at least a same plane as said major surface of said semiconductor region along said at least upper regions of side walls of said semiconductor region.
3 more elements
Dependencies are inferred from the claim text.