EPROM in high density CMOS having added substrate diffusion

A method of making an EPROM transistor in a CMOS integrated circuit made with a process having two micron or less design rules, comprising the steps of:

• forming a matrix of field oxide on a surface of a semiconductive substrate, said matrix delineating a plurality of active areas that are spaced on said surface by said field oxide;
• forming a well of one conductivity type in an active area portion of opposite conductivity type in said substrate;
• said well extending into said substrate from said surface;
• forming a first doped region of opposite conductivity type on an active area of said substrate, which first region is large enough in surface area to serve as a bottom plate of a substrate to poly capacitor;
• forming a second doped region of opposite conductivity type on an active area of said substrate, which second region will provide a first capacitance with an overlying floating gate of an EPROM;
• forming a dielectric coating of MOS transistor gate dielectric thickness on at least said active areas of said surface;
• depositing a blanket layer of gate electrode material over said dielectric coating;
• defining said blanket layer of gate electrode material into gate electrodes for complementary MOS transistors, an upper plate for a substrate to poly capacitor, and a floating gate for an EPROM MOS transistor, said floating gate electrode having an integral extension that extends from a channel area of said EPROM onto said dielectric coating covering said second doped region, said floating gate extension being enlarged over said second doped region so that it substantially covers said second doped region and capacitance between said floating gate and said second doped region is at least about double capacitance between said floating gate and said substrate;
• forming source and drain regions for said MOS transistors under said dielectric coating at opposed edges of said gate electrodes including said floating gate electrode, with the source and drain regions being of opposite conductivity type from the substrate surface in which they are disposed;
• forming a blanket dielectric coating on said substrate over said gate electrodes;
• forming appropriate conductive connections to said source and drain regions, said first and second doped regions in said substrate, and to said MOS gate electrodes but not to said floating gate electrode,
• effective to make an EPROM in said CMOS integrated circuit that has an electrically floating gate that can be charged at voltages handled by said MOS transistors in said integrated circuit.

An integrated circuit that has one gate electrode layer, MOS transistors, a substrate to gate electrode material capacitor and at least one EPROM transistor, said integrated circuit comprising:

• MOS transistors on a surface of a semiconductive substrate, said MOS transistors having channel lengths less than about two microns;
• at least one substrate to gate electrode material capacitor on an area of said substrate, said capacitor comprising a first region of said substrate doped to opposite conductivity type, a dielectric layer, and an overlying layer of gate electrode material;
• at least one EPROM transistor on an area of said substrate, with the EPROM transistor having an electrically floating gate electrode, said floating gate electrode having an integral extension that extends from a channel area of said EPROM onto a dielectric coating covering a second region of said substrate doped to opposite conductivity type, said floating gate extension being enlarged as compared to said EPROM channel area so that it substantially covers said second doped region and capacitance between said floating gate and said second doped region is at least about double capacitance between said floating gate and said substrate;
• effective to allow the EPROM transistor to be made along with the MOS transistors and the capacitor by merely incorporating changes in masks used to make said integrated circuit, and the floating gate of the EPROM can be charged at low voltages that can be handled by said MOS transistors.