Integrated photosensing device for active pixel sensor imagers

An integrated imaging array having a plurality of sets of array sites, each array site comprising:

• a photosensing device including a semiconductor substrate, a junction diode having a first electrical side and a second electrical side, and a Metal-Oxide-Semiconductor (MOS) capacitor having a first electrical side and a second electrical side, said junction diode and said MOS capacitor being adjacently integrated on said substrate, said photosensing device further including a body terminal contacting a region of said substrate, said region being defined by said first electrical side of said junction diode and said first electrical side of said MOS capacitor, a gate terminal contacting said second electrical side of said MOS capacitor, and a diode terminal contacting said second electrical side of said junction diode;
• and
• a first switch means coupled to said diode terminal of said photosensing device,
• said MOS capacitor being operable to be biased into a first mode during a first phase in response to a first voltage signal applied between said gate terminal and said body terminal,
• said junction diode being operable to be reverse biased during said first phase in response to a second voltage signal applied between said diode terminal and said body terminal,
• said MOS capacitor being further operable to be biased into a second mode during a second phase in response to a third voltage signal applied between said gate terminal and said body terminal, said second phase continuing for a given time interval, said photosensing device being operable to be illuminated during said given time interval,
• said MOS capacitor being further operable to be biased into said first mode during a third phase in response to a fourth voltage signal applied between said gate terminal and said body terminal, wherein said first mode is an accumulation mode,
• said photosensing device being operable to generate a voltage response between said diode terminal and said body terminal during said second phase, said photosensing device being further operable to boost said voltage response during said third phase.

An integrated imaging array having a plurality of sets of array sites, each array site comprising:

• a photosensing device including a semiconductor substrate, a junction diode having a first electrical side and a second electrical side, and a Metal-Oxide-Semiconductor (MOS) capacitor having a first electrical side and a second electrical side, said junction diode and said MOS capacitor being adjacently integrated on said substrate, said photosensing device further including a body terminal contacting a region of said substrate, said region being defined by said first electrical side of said junction diode and said first electrical side of said MOS capacitor, a gate terminal contacting said second electrical side of said MOS capacitor, and a diode terminal contacting said second electrical side of said junction diode, said MOS capacitor being operable to be biased into a first mode during a first phase, said junction diode being operable to be reverse biased during said first phase, said MOS capacitor being further operable to be biased into a second mode during a second phase, said second phase continuing for a given time interval, said photosensing device being operable to be illuminated during said given time interval, said MOS capacitor being further operable to be biased into said first mode during a third phase, said photosensing device being operable to generate a voltage response between said diode terminal and said body terminal during said second phase, said photosensing device being further operable to boost said voltage response during said third phase;
• a first switch means coupled to said diode terminal of said photosensing device;
• a source follower circuit including
• a Metal-Oxide-Semiconductor (MOS) field effect transistor having a source terminal, a drain terminal, and a gate terminal, said gate terminal of said MOS field effect transistor being coupled to said diode terminal of said photosensing device, said source terminal being coupled to said gate terminal of said photosensing device, and
• a current-source load coupled between said source terminal of said MOS field effect transistor and said body terminal of said photosensing device,
• said source follower circuit being operable to buffer said voltage response;
• a second switch means coupled to said source terminal of said MOS field effect transistor and to said gate terminal of said photosensing device;
• an output node comprising a first node portion and a second node portion, said first node portion being common to said source terminal of said MOS field effect transistor and said gate terminal of said photosensing device, said second node portion being common to said current-source load and one side of said second switch means;
• and
• a third switch means coupled between said first node portion and said second node portion,
• wherein each array site in one of said plurality of sets is operable during said first and third phase to be sequentially addressed by closing said third switch means, and wherein each array site in one of said plurality of sets is further operable to time share said second node portion when addressed.