Resizable and relocatable memory scratch pad as a cache slice
AssigneeSamsung Electronics Co., Ltd.
InventorsMoataz A. Mohamed, Heonchul Park
Life of this patent
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Abstract
A cache system supports a re-sizable software-managed fast scratch pad that is implemented as a cache-slice. A processor register indicates the size and base address of the scratch pad. Instructions which facilitate use of the scratch pad include a prefetch instruction which loads multiple lines of data from external memory into the scratch pad and a writeback instruction which writes multiple lines of data from the scratch pad to external memory. The prefetch and writeback instructions are non-blocking instructions to allow instructions following in the program order to be executed while a prefetch or writeback operation is pending.
Claims11
A cache comprising:
- a memory and
- control circuitry which controls access to the memory, wherein the control circuitry is configurable so that a first portion of the memory is accessible as a cache memory at the same time that a second portion of the memory section is accessible as a scratch pad, and wherein the control circuitry comprises:
- a tag memory;
- and
- an address pipeline which receives input address signals;
- generates from an address signal corresponding to the second portion of the memory an index identifying a storage location in the second portion of the memory;
- and routes an address signal not corresponding to the second portion of the memory to the tag memory for a hit/miss calculation.
A cache system comprising:
- a memory that includes a plurality of memory sections, wherein each memory section includes multiple lines and each memory section is individually configurable for use in a cache memory or in a scratch pad memory;
- a tag memory that includes a plurality of tag sections, wherein each tag section corresponds to one of the memory sections and includes multiple entries, each entry corresponding to one of the lines in the memory section that corresponds to the tag section containing the entry;
- hit/miss logic coupled to the tag memory, wherein the hit/miss logic compares at least a portion of an input address to information in the entries to match an entry with the input address, the hit/miss logic generating an index to identify the line that corresponds to the entry matched to the input address;
- and
- an address pipeline adapted to receive the input address and to generate an internal address for accessing the memory, wherein:
- in response to the input address being within a range of addresses corresponding to the scratch pad memory, the address pipeline generates the internal address from the input address to access one of the memory sections that is configured for use in the scratch pad memory;
- and
- in response to the input address being outside the range of addresses corresponding to the scratch pad memory, the address pipeline uses the index from the hit/miss logic in generating the internal address to access one of the memory sections that is configured for use in the cache memory.
Dependencies are inferred from the claim text.