Optimizing data movement with hardware operations
AssigneeHewlett-Packard Company
InventorTony M. Brewer
Life of this patent
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Abstract
In a computer system, an architecture for optimizing aspects of data movement operations by performing functions such as memory allocation and notification on hardware rather than software. The invention thereby optimizes several higher-level processor operations that involve data movement, including internodal messaging, data copying, and data zeroing. Method and apparatus is also disclosed for detecting and responding to translation lookaside buffer (TLB) purges indicating a change in physical memory mapping during translation of virtual memory to physical memory.
Claims22
A method for optimizing data movement in a computer system, comprising the steps of:
- (a) receiving a request from a device to perform a data movement operation;
- (b) allocating memory space to enable the operation;
- (c) moving the data;
- (d) upon completion of step (c), notifying the device that the operation is complete;
- and
- (e) performing selected ones of steps (b) and (d) as hardware operations.
A method for optimizing data movement in a computer system, comprising the steps of:
- (a) receiving a request from a processor to perform a data movement operation;
- (b) allocating memory space to enable the operation;
- (c) moving the data;
- (d) upon completion of step (c), notifying the processor that the operation is complete;
- and
- (e) performing steps (b) and (d) as hardware operations, said hardware comprising a processor agent operatively responsive to the processor and a memory access controller responsively operative to the processor agent, wherein the processor agent includes:
- a message/copy state machine;
- a set of input registers receiving data from the processor and supplying data to the message/copy state machine;
- and
- a status queue receiving data from the message/copy state machine and supplying data to the processor;
- and wherein the memory access controller includes:
- a message allocation state machine;
- and
- a message completion status queue.
An architecture configuration disposed to optimize data movement operations by enabling selected data movement operations with hardware rather than software, comprising:
- a processor agent, the processor agent including:
- first input registers receiving data from a first processor and second input registers receiving input from a second processor;
- a message/copy state machine receiving control information from the input registers;
- a data mover;
- means for pipelining discrete data movement operations;
- a first status queue receiving first control information from the message/copy state machine and dispensing said first control information to the first processor;
- and
- a second status queue receiving second control information from the message/copy state machine and dispensing said second control information to the second processor.
Hardware for optimizing data movement operations, comprising:
- means for receiving a request from a device to perform a data movement operation;
- means for allocating memory space to enable the operation;
- means for moving the data;
- and
- means, responsive to said means for moving, for notifying the device that the operation is complete.
An improved method for optimizing data movement operations in which said method comprises the steps of (a) receiving a request from a device to perform a data movement operation;
- (b) allocating memory space to enable the operation;
- (c) moving the data;
- and (d) upon completion of step (c), notifying the device that the operation is complete, wherein the improvement comprises:
- performing selected ones of steps (b) and (d) as hardware operations.
Dependencies are inferred from the claim text.