Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device

A method of providing cacheable memory in a device coupled to an I/O bus in a computer system having central processing unit (CPU) complex and an expansion bus in circuit communication with the CPU complex and having at least one expansion memory device coupled thereon;

• the CPU complex comprising:
• a cache;
• a system bus;
• an input/output (I/O) bus;
• and
• a bus interface unit coupled between said system bus and said I/O bus) the method comprising the steps of:
• (a) identifying memory locations in said expansion memory devices which are cacheable;
• (b) monitoring transmissions on said I/O bus and said expansion bus to determine when a data write operation to a cacheable memory location in said expansion memory device has occurred and the address of the cacheable memory location being written into;
• and
• (c) writing the address of said cacheable memory location being written into on the system bus when said location is identified and the system bus is available.

A computer system containing:

• a central processing unit (CPU), a cache coupled to said CPU, and system memory coupled to said CPU;
• said computer system further comprising:
• (a) an input/output (I/O) bus for connecting said computer system to I/O devices and to expansion memory devices on an expansion bus;
• said I/O bus supporting memory data transfers between said I/O devices and said cache, I/O and memory data transfers between pairs of said I/O devices, and I/O and memory data transfers between pairs of said expansion memory devices, and said memory data transfers between said I/O devices and said cache including data transfers between cacheable memory locations contained in said I/O devices and memory locations contained in said cache, and said memory data transfers between said pairs of I/O devices including data transfers between one I/O device controlling said I/O bus and cacheable memory locations contained in another I/O device, and said memory data transfers between pairs of expansion memory devices including data transfers between one expansion memory device controlling said expansion bus and cacheable memory locations contained in another expansion memory device;
• (b) a bus interface unit coupled between said I/O bus and said cache;
• said bus interface unit comprising:
• (1) means for identifying said cacheable memory locations contained in said I/O devices and said expansion memory devices;
• (2) bus snooping logic, in circuit communication with said I/O bus, said expansion bus, and said means for identifying said cacheable memory locations, for monitoring said memory data transfers on said I/O bus between pairs of said I/O devices and for monitoring said memory data transfers on said expansion bus between pairs of said expansion memory devices, and detecting when data is being written by said one I/O device controlling said I/O bus to a cacheable memory location contained in said another I/O device, and detecting when data is being written by said one expansion memory device controlling said expansion bus to a cacheable memory location contained in said another expansion memory device;
• and
• (3) invalidation signaling logic means responsive to detection by said bus snooping logic that data is being written by said one expansion memory device to a cacheable memory location contained in another said expansion memory device for directing an invalidation signal to said cache;
• said invalidation signal including the address of the cacheable memory location in said another expansion memory device to which data is being written and serving to cause invalidation of a location in said cache corresponding to said address if said cache currently contains a location corresponding to said address.