Serial programming mode for non-volatile memory

A method for programming a non-volatile memory device, said method comprising:

• asserting a clock signal at a clock input of the memory device;
• asserting at a serial input of the memory device a first sequence of bits, each bit of the first sequence of bits being clocked into the memory device at a respective transition of the clock signal;
• asserting at the serial input of the memory device a second sequence of bits, each bit of the second sequence of bits being clocked into the memory device at a respective transition of the clock signal;
• and
• asserting at the serial input of the memory device a first control bit and a second control bit, the first control bit having a first state indicating that the first sequence of bits represents a store command, the second control bit having a second state indicating that the second sequence of bits represents a value to be stored in the memory device, the first and second control bits being clocked into the memory device at a respective transition of the clock signal.

A non-volatile semiconductor memory device comprising:

• a plurality of data pins to receive the respective conductors of a parallel data bus;
• a mode activation circuit to activate a serial input of said memory device in response to a request to enter a serial interface mode;
• a clock input to receive a clock signal;
• and
• a shift register circuit to receive a sequence of bits via the serial input, each bit of the sequence of bits being received in the memory device at a respective transition of the clock signal, the sequence of bits including a plurality of control bits, each control bit indicating whether a respective portion of the sequence of bits is a device control value or a data value.

An apparatus comprising:

• a bus including a plurality of address conductors;
• a processor coupled to said bus;
• and
• a non-volatile memory device coupled to said bus, said memory device including:
• a plurality of address pins to receive the respective conductors of the plurality of address conductors;
• a mode activation circuit to activate a serial input of said memory device in response to a request to enter a serial interface mode;
• a clock input to receive a clock signal;
• and
• a shift register circuit to receive a sequence of bits via the serial input, each bit of the sequence of bits being received in the memory device at a respective transition of the clock signal, the sequence of bits including a plurality of control bits, each control bit indicating whether a respective portion of the sequence of bits is a device control value or a data value.