Method and apparatus for controlling multiple dice with a single die
AssigneeIntel Corporation
InventorsGurbir Singh, Konrad K. Lai
Life of this patent
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Abstract
A method and apparatus for controlling an integrated circuit (IC) die with another IC die. The present invention uses a processor to control the operation of a cache memory die. In this manner, the cache memory is directed by the processor as to the operations to be performed, such as writing to the cache memory. A dedicated bus is coupled between the two dice. This dedicated bus is used to send control and other signals between the two dice.
Claims15
A method of controlling a first cache memory coupled to a bus using a processor coupled to the bus, wherein the first cache memory comprises decode and control logic, wherein the processor has a second cache memory and a cache controlling logic to control both the first and second cache memories, said method comprising:
- the cache controlling logic specifying at least one operation in an encoded form as at least one micro-operation code;
- the cache controlling logic transferring said at least one micro-operation code to the first cache memory on the bus;
- the decode and control logic decoding said at least one micro-operation code to identify said at least one operation;
- and
- the decode and control logic performing said at least one operation by generating signals to initiate access cycles to the first cache memory.
A computer system comprising:
- a first cache memory;
- a processor having a second cache and a cache controlling logic to control the first and second caches;
- a bus coupled between the processor and the first cache memory to transfer information between the processor and the first cache memory;
- wherein the cache controlling logic controls the first cache memory using micro-operation codes representing encoded operations that are transferred to the first cache memory via the bus to specify cache memory operations;
- and further wherein the first cache memory comprises decode and control logic to decode each micro-operation code to perform operations associated with decoded micro-operation codes, the decode and control logic providing signals to initiate access cycles to the first cache memory in response to the decoding.
A computer system comprising:
- a bus;
- a first cache memory coupled to the bus;
- a processor having a second cache memory and cache controlling logic to control the first and second cache memories coupled to the bus,
- wherein the second cache memory comprises decode and control logic to decode micro-operation codes, representing encoded cache memory operations that are transferred to the first cache memory from the cache controlling logic of the processor via the bus, to perform operations associated with decoded micro-operation codes, the decode and control logic providing signals to initiate access cycles to the first cache memory in response to the decoding.
A method of controlling a first cache memory coupled to a bus using a device coupled to the bus, the device having a second cache memory and cache controlling logic to control the first and second cache memories said method comprising:
- the cache memory receiving from the cache controlling logic via the bus at least one micro-operation code specifying at least one operation;
- decode and control logic in the first cache memory decoding said at least one micro-operation code to identify said at least one operation;
- and
- the decode and control logic performing said at least one operation by generating signals to initiate access cycles to the first cache memory.
Dependencies are inferred from the claim text.