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US 5,966,720 AGranted
Flash memory accessed using only the logical address
AssigneeFujitsu Limited
InventorsHiroyuki Itoh, Noriyuki Matsui
Life of this patent
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AssigneeFujitsu Limited
InventorsHiroyuki Itoh, Noriyuki Matsui
Estimating the term…
A flash memory control apparatus and method which enables updating of data at high speed. The flash memory control apparatus includes a flash memory having a memory region which is divided into a plurality of sectors each including a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data; and a control device, coupled to the flash memory, for making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. The flash memory control method includes the steps of: (a) dividing a memory region of a flash memory into a plurality of sector; and (b) making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. Each of the sectors includes a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data
A method of controlling a flash memory having a plurality of blocks, said flash memory being erased by a minimum unit of one block, said method comprising the steps of:
A memory device, comprising:
A memory controller for controlling a memory device having a flash memory including a plurality of blocks, each of said blocks being divided into a plurality of sectors each including a storage portion for storing at least a logical address of the sector and a data part for storing data, said flash memory being erased by a minimum unit of one block, said memory controller comprising:
Dependencies are inferred from the claim text.