Reduction of poly depletion in semiconductor integrated circuits
AssigneeAdvanced Micro Devices, Inc.
InventorEmi Ishida
Life of this patent
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AssigneeAdvanced Micro Devices, Inc.
InventorEmi Ishida
Estimating the term…
A method of forming a transistor includes the steps of forming a gate structure (56) overlying a gate oxide layer (54), wherein the gate structure (56) and gate oxide layer (54) overlie a substrate (50), thereby separating the substrate (50) into a first region (90) and a second region (92) with a channel region therebetween. The method also includes doping the gate structure (56), the first region (90) and the second region (92) and annealing the doped gate structure (56) with a laser anneal, thereby driving the dopant through a substantial depth of the gate structure (56). Lastly, a source region (94) and a drain region (96) are formed in the first region (90) and the second region (92), respectively, wherein the dopant is further driven into the gate structure (56). Consequently, the dopant is driven substantially deeper in the gate structure (56) than in the shallow source region (94) and drain region (96) junctions to allow decoupling of poly depletion from the need for shallow junctions.
A method of forming a transistor, comprising the steps of:
A method of forming a transistor, comprising the steps of:
Dependencies are inferred from the claim text.