Back to results
US 5,966,597 AGranted
Method of forming low resistance gate electrodes
AssigneeAltera Corporation
InventorPeter J. Wright
Life of this patent
Estimating the term…
Abstract
Provided is a transistor device, and a process for fabricating such a device, in which a top portion of a polysilicon gate electrode is removed and replaced by a low resistance metal material using a damascene process. Gate electrodes in accordance with the present invention provide improved conductivity over conventional polysilicon and silicide-capped polysilicon gate electrodes, due to the low resistivity of the metal, but do not have the drawbacks associated with the complete removal and replacement of polysilicon with a metal.
Claims20
A method of forming a semiconductor device, comprising:
- forming a first dielectric layer over a partially-processed semiconductor wafer having an initial gate electrode comprising polysilicon, said initial gate electrode having a top surface;
- planarizing said dielectric to expose the top surface of said initial gate electrode;
- selectively removing a top portion of said initial gate electrode;
- depositing a low resistance material over said partially-processed semiconductor wafer, said low resistance material having a lower resistance than said initial gate electrode;
- and
- planarizing said low resistance material to expose the top surface of said first dielectric layer;
- whereby a low resistance gate electrode is formed, said low resistance gate electrode having a top portion comprising the low resistance material.
4 more elements
Dependencies are inferred from the claim text.